TMS570LS3137_12 Datasheet, PDF (146/159 Pages) Texas Instruments – TMS570LS3137 16/32-Bit RISC Flash Microcontroller

TMS570LS3137
SPNS162. – SEPTEMBER 2011
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Table 5-24. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)^(1)(2)(3)
NO.
1 t_c(SPC)M
2 ⁽⁵⁾ t_w(SPCH)M
t_w(SPCL)M
3 ⁽⁵⁾ t_w(SPCL)M
t_w(SPCH)M
4 ⁽⁵⁾ t_{v(SIMO-SPCH)M}
t_{v(SIMO-SPCL)M}
5 ⁽⁵⁾ t_{v(SPCH-SIMO)M}
t_{v(SPCL-SIMO)M}
6 ⁽⁵⁾ t_{su(SOMI-SPCH)M}
t_{su(SOMI-SPCL)M}
7 ⁽⁵⁾ t_{v(SPCH-SOMI)M}
t_{v(SPCL-SOMI)M}
8 ⁽⁶⁾ t_C2TDELAY
9 ⁽⁶⁾ t_T2CDELAY
10 t_SPIENA
11 t_SPIENAW
Parameter
Cycle time, SPICLK ⁽⁴⁾
Pulse duration, SPICLK high (clock
polarity = 0)
Pulse duration, SPICLK low (clock
polarity = 1)
Pulse duration, SPICLK low (clock
polarity = 0)
Pulse duration, SPICLK high (clock
polarity = 1)
Valid time, SPICLK high after
SPISIMO data valid (clock polarity =
0)
Valid time, SPICLK low after
SPISIMO data valid (clock polarity =
1)
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
Setup time CS
active until SPICLK
high (clock polarity =
0)
CSHOLD = 0
CSHOLD = 1
Setup time CS
active until SPICLK
low (clock polarity =
1)
CSHOLD = 0
CSHOLD = 1
Hold time SPICLK low CS until
inactive (clock polarity = 0)
Hold time SPICLK high until CS
inactive (clock polarity = 1)
SPIENAn Sample Point
SPIENAn Sample point from write to
buffer
MIN
40
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M – t_f(SPC)M – 3
0.5t_c(SPC)M – t_f(SPC)M – 3
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M – 5
0.5t_c(SPC)M – 5
0.5t_c(SPC)M – t_r(SPC) – 3
0.5t_c(SPC)M – t_f(SPC) – 3
t_r(SPC)
t_f(SPC)
5
5
0.5*t_c(SPC)M +
(C2TDELAY+2) * t_c(VCLK) -
t_f(SPICS) + t_r(SPC) – 15
0.5*t_c(SPC)M +
(C2TDELAY+3) * t_c(VCLK) -
t_f(SPICS) + t_r(SPC) – 15
0.5*t_c(SPC)M +
(C2TDELAY+2) * t_c(VCLK) -
t_f(SPICS) + t_f(SPC) – 15
0.5*t_c(SPC)M +
(C2TDELAY+3) * t_c(VCLK) -
t_f(SPICS) + t_f(SPC) – 15
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_f(SPC) + t_r(SPICS) -
4
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_r(SPC) + t_r(SPICS) -
4
(C2TDELAY+1)* t_c(VCLK) -
t_f(SPICS) – 25
MAX
256t_c(VCLK)
0.5t_c(SPC)M + 3
0.5t_c(SPC)M + 3
0.5t_c(SPC)M + 3
0.5t_c(SPC)M + 3
0.5*t_c(SPC)M +
(C2TDELAY+2) * t_c(VCLK) -
t_f(SPICS) + t_r(SPC) + 3
0.5*t_c(SPC)M +
(C2TDELAY+3) * t_c(VCLK) -
t_f(SPICS) + t_r(SPC) + 3
0.5*t_c(SPC)M +
(C2TDELAY+2) * t_c(VCLK) -
t_f(SPICS) + t_f(SPC) + 3
0.5*t_c(SPC)M +
(C2TDELAY+3) * t_c(VCLK) -
t_f(SPICS) + t_f(SPC) + 3
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_f(SPC) + t_r(SPICS) +
8
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_r(SPC) + t_r(SPICS) +
8
(C2TDELAY+1)*t_c(VCLK)
(C2TDELAY+2)*t_c(VCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) t_c(VCLK) = interface clock cycle time = 1 / f_(VCLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)M ≥ (PS +1)t_c(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t_c(SPC)M = 2t_c(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
146 Peripheral Information and Electrical Specifications
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