LM3S102 Datasheet, PDF (145/487 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S102 Microcontroller
5.3 Initialization and Configuration
The PLL is configured using direct register writes to the RCC register. The steps required to
successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source and allows
for the new PLL configuration to be validated before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN and OEN
bits in RCC. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN and OEN bits powers and enables the PLL and its
output.
3. Select the desired system divider (SYSDIV) in RCC and set the USESYS bit in RCC. The SYSDIV
field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC.
Note: If the BYPASS bit is cleared before the PLL locks, it is possible to render the device unusable.
5.4 Register Map
Table 5-6 on page 145 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 5-6. System Control Register Map
Offset Name
Type
Reset
Description
0x000 DID0
0x004 DID1
0x008 DC0
0x010 DC1
0x014 DC2
0x018 DC3
0x01C DC4
0x030 PBORCTL
0x034 LDOPCTL
0x040 SRCR0
0x044 SRCR1
0x048 SRCR2
RO
-
Device Identification 0
RO
-
Device Identification 1
RO
0x0007.0003 Device Capabilities 0
RO
0x0000.901F Device Capabilities 1
RO
0x0103.1011 Device Capabilities 2
RO
0x8300.01C0 Device Capabilities 3
RO
0x0000.0007 Device Capabilities 4
R/W
0x0000.7FFD Power-On and Brown-Out Reset Control
R/W
0x0000.0000 LDO Power Control
R/W
0x00000000 Software Reset Control 0
R/W
0x00000000 Software Reset Control 1
R/W
0x00000000 Software Reset Control 2
See
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July 14, 2014
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Texas Instruments-Production Data