TLC3574_14 Datasheet, PDF (14/50 Pages) Texas Instruments – 14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578

TLC3574, TLC3578, TLC2574, TLC2578
5ĆV ANALOG, 3Ć/5ĆV DIGITAL, 14Ć/12ĆBIT, 200ĆKSPS, 4Ć/8ĆCHANNEL
SERIAL ANALOGĆTOĆDIGITAL CONVERTERS WITH ±10ĆV INPUTS
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
timing requirements over recommended operating free-air temperature range, AV_DD = 5 V,
DV_DD = 5 V, V_REFP = 4 V, V_REFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CS trigger
PARAMETERS
MIN
tsu(2) Setup time, CS falling edge before SCLK rising edge, at 25-pF load
12
td(4)
Delay time, delay time from the falling edge of 16th SCLK to CS rising edge, at 25 pF load
(see Note 12)
5
tw(2) Pulse width of CS high, at 25-pF load
1
td(5)
Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%
final level), at 10 pF load
DVDD = 5 V
DVDD = 2.7 V
0
0
td(6) Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load
0
td(7) Delay time, delay from CS falling edge to INT rising edge, at 10-pF load
DVDD = 5 V
0
DVDD = 2.7 V
0
† _{Specified by design}
NOTE 12: For normal short sampling, td(4) is the delay time from the falling edge of 16th SCLK to CS rising edge.
For normal long sampling, td(4) is the delay time from the falling edge of 48th SCLK to CS rising edge.
TYP MAX UNIT
ns
ns
tc(1)
12
30† ^ns
6 ns
6
16† ^ns
CS
VIH
VIL
tsu(2)
td(4)
tw(2)
SCLK
1
16
SDI
SDO
Don’t Care
td(5)
Hi-Z
ID15 ID1
ID0
OD15 OD1 OD0
Don’t Care
Hi-Z
Don’t Care
OD15
td(6)
OD7 ^Hi-Z
EOC
OR
INT
td(7)
− − − − The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 2. Critical Timing for CS Trigger
14
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