TIBPAL20L8-7C_15 Datasheet, PDF (14/28 Pages) Texas Instruments – HIGH-PERFORMANCE IMPACT-X

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TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X ™ PAL^® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V_CC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
V_CC
4V
5V
Active Low
Registered Output
CLK
t_pd^†
(600 ns TYP, 1000 ns MAX)
1.5 V
t_su^‡
1.5 V
t_w
V_OH
V_OL
V_IH
1.5 V
V_IL
† _{This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.}
‡ _{This is the setup time for input or feedback.}
Figure 2. Power-Up Reset Waveforms
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