SN65LVDS822 Datasheet, PDF (14/27 Pages) Texas Instruments – FLATLINK LVDS RECEIVER

SN65LVDS822
SLLSEE8A – SEPTEMBER 2013 – REVISED OCTOBER 2013
www.ti.com
XXX
XXX
CLKOUT
20%
t_SU2
t_H2
80%
80%
D[26:0]
20%
20%
Figure 3. CMOS Output Timing (CLKPOL = Low)
80%
CLKOUT
t_SU2
t_H2
80%
80%
D[26:0]
20%
20%
Figure 4. CMOS Output Timing (CLKPOL = High)
14
Submit Documentation Feedback
Product Folder Links :SN65LVDS822
Copyright © 2013, Texas Instruments Incorporated