SN65LVDS822 Datasheet, PDF (1/27 Pages) Texas Instruments – FLATLINK LVDS RECEIVER

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SN65LVDS822
SLLSEE8A – SEPTEMBER 2013 – REVISED OCTOBER 2013
FLATLINK™ LVDS RECEIVER
Check for Samples: SN65LVDS822
FEATURES
1
•2 4:27 LVDS-to-CMOS Deserializer
• Pixel Clock Range of 4 MHz to 54 MHz, for
Resolutions of 160x120 to 1024x600
• Special 2:27 Mode With 14x Sampling Allows
Using Just 2 Data Lanes
• Very Low EMI With 3-Way Selectable CMOS
Slew Rate
• Supports Single 3.3 V Power Supply; V_DDIO
Allows 1.8 V – 3.3 V for Flexible Panel Support
• Clock Output is Rising or Falling Edge
• Bus-Swap Feature for Flexible PCB Layout
• Integrated Switchable Input Termination
• All Input Pins are Failsafe; ±3 kV HBM ESD
Protection
• 7 mm x 7 mm 48-pin QFN with 0.5 mm pitch
• Compatible With TIA/EIA-644-A Transmitters
APPLICATIONS
• Printers
• Appliances With an LCD
• Digital Cameras
DESCRIPTION
The SN65LVDS822 is an advanced FlatLink™ LVDS receiver designed on a modern CMOS process. It has
several unique features, including three selectable CMOS output slew rates, CMOS output voltage support of
1.8 V to 3.3 V, a pinout swap option, integrated differential termination (configurable), an automatic low-power
mode, and deserialization modes of 4:27 and 2:27. It is compatible with TI FlatLink™ transmitters such as the
SN75LVDS83B, SN65LVDS93A, and standard industry LVDS transmitters that comply with TIA/EIA-644-A.
The SN65LVDS822 implements five low-voltage differential signal (LVDS) line receivers: 4 data lanes and 1
clock lane. The clock is internally multiplied by 7 or 14 (depending on pin MODE14), and used for sampling
LVDS data. The device operates in either 4-lane 7x mode, or 2-lane 14x mode. Each input lane contains a shift
register that converts serial data to parallel. 27 total bits per clock period are deserialized and presented on the
CMOS output bus, along with a clock that uses either rising- or falling-edge alignment.
A clock frequency range of 4 MHz to 54 MHz is supported in the standard 7x mode, which is to be used with
LVDS data rates of 28 Mbps to 378 Mbps. The 14x mode supports 4 MHz to 27 MHz, for LVDS data rates of
56 Mbps to 378 Mbps. The LVDS clock frequency always matches the CMOS output clock frequency. DC
common mode voltage is monitored on clock line for normal operation. The device is designed to support
resolutions as low as 1/16th VGA (160x120), and as high as 1024x600, with 60 frames per second and 24-bit
color.
LV DS
LVDS
822
LCD CMOS
RGB
Driver
FFC
SoC
LVDS CMOS Video
LVDS _Serializer RGB _Source
Can be discrete
SN75LVDS83B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FLATLINK is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated