LMH2180SDE Datasheet, PDF (14/18 Pages) Texas Instruments – LMH2180 75 MHz Dual Clock Buffer

PHASE NOISE
A clock buffer adds noise to the clock signal. This noise caus-
es uncertainty in the phase of the clock signal. This uncer-
tainty is described by jitter (time domain) or phase noise
(frequency domain). Communication systems, such as Wire-
less LAN, require a low jitter/phase noise clock signal to
obtain a low Bit Error Rate. Figure 4 shows the frequency do-
main representation of a clock signal with frequency f_C. With-
out Phase Noise the entire signal power would only be located
at the frequency f_C. Phase Noise spreads some of the power
to adjacent frequencies. Phase Noise is usually specified in
dBc/Hz at a given frequency offset Δf from the carrier, where
dBc is the power level in dB relative to the carrier. The noise
power is measured within a 1 Hz bandwidth.
Figure 5 shows the setup used to measure the LMH2180
phase noise. The clock driving the LMH2180 is a state of the
art 38.4MHz TCXO. Both the TCXO phase noise and the
phase noise at the LMH2180 output were measured. At offset
frequencies of 1 kHz and higher from the carrier, the TCXO
phase noise is sufficiently low to accurately calculate the
LMH2180 contribution to the phase noise at the output. The
LMH6559, whose phase noise contribution can be neglected,
is used to drive the 50Ω input impedance of the Signal Source
Analyzer.
LAYOUT DESIGN RECOMMENDATION
Careful consideration during circuit design and PCB layout
will eliminate problems and will optimize the performance of
the LMH2180. It is best to have the same ground plane on the
PCB for all decoupling and other ground connections.
To ensure a clean supply voltage it is best to place decoupling
capacitors close to the LMH2180, between V_DD and V_SS.
Another important issue is the value of the components, be-
cause this also determines the sensitivity to disturbances.
Resistor values have to be low enough to avoid a significant
noise contribution and large enough to avoid a significant in-
crease in power consumption while loading inputs or outputs
to heavily.
FIGURE 4. Phase Noise
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FIGURE 5. Measurement Setup
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