DLKPC192S Datasheet, PDF (14/25 Pages) Texas Instruments – 10-Gbps ETHERNET LAN PHYSICAL CODING SUBLAYER (PCS) WITH SSTL XGMII INTERFACE

DLKPC192S
10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER (PCS)
WITH SSTL XGMII INTERFACE
SLLS536 − AUGUST 2002
Table 7. Vendor Unique Registers
REGISTER ADDRESS
16
17
18
19
20−31
REGISTER NAME
Transmitter status
Receive status
TX and RX control
Test mode control
Reserved
Table 8. Transmitter Status Bit Definitions (Register 16)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
16.15
TXI_OVFL Transmit FIFO has detected an overflow error. Event is latched to ensure observability.
Read-only
Self-clearing
16.14
TXI_UNFL Transmit FIFO has detected an underflow error. Event is latched to ensure observability.
Read-only
Self-clearing
16.13
TXI_DEL Transmit FIFO has detected movement toward overflow which should result in an automatic Read-only
deletion. Event is latched to ensure observability. This is not an indication of an error.
Self-clearing
16.12
TXI_INS
Transmit FIFO has detected movement toward underflow which should result in an automatic Read-only
insertion. Event is latched to ensure observability. This is not an indication of an error.
Self-clearing
16.11:10 Reserved First read always returns 01. Subsequent reads are indeterminate.
Read-only
Self-clearing
16.9:0
Reserved Read returns 0.
NOTE: Power-on reset value: 0x0400.
Read-only
Table 9. Receiver Status Bit Definitioins (Register 17)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
17.15
RXO_OVFL
Receive FIFO has detected an overflow error. Event is latched to ensure observability.
Read-only
Self-clearing
17.14
RXO_UNFL
Receive FIFO has detected an underflow error. Event is latched to ensure observability. Read-only
Self-clearing
17.13
RXO_DEL
Receive FIFO has detected movement toward overflow which should result in an automatic Read-only
deletion. Event is latched to ensure observability. This is not an indication of an error.
Self-clearing
17.12
RXO_INS
Receive FIFO has detected movement toward underflow which should result in an Read-only
automatic insertion. Event is latched to ensure observability. This is not an indication of an Self-clearing
error.
17.11:10 Reserved
First read always returns 01. Subsequent reads are indeterminate
Read-only
Self-clearing
17.9
RXG_HIBER_SAV 64/66b bit error rate (BER > 10E−4). The occurrence of this condition does not cause the Read-only
receive state machine to transition to the RX_INIT state and it does not output line fault Self-clearing
characters on the XGMII receive interface.
17.8:1
RXG_ERR_CNT
Frame-sync BER count. Contains the value from the most recent 250-µs count period. Read-only
Changes automatically once every 250 µs
Self-clearing
17.0
Reserved
Read returns 0.
NOTE: Power-on reset value: 0x0400.
Read-only
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