LM3S9D92 Datasheet, PDF (1390/1407 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Register Quick Reference
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1
0
ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 1134)
TOEN
ASRCP
ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 (see page 1134)
TSLVAL
TSEN
ISLVAL
ISEN
CINV
TOEN
ASRCP
ACCTL2, type R/W, offset 0x064, reset 0x0000.0000 (see page 1134)
TSLVAL
TSEN
ISLVAL
ISEN
CINV
TOEN
ASRCP
Pulse Width Modulator (PWM)
PWM0 base: 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 1151)
TSLVAL
TSEN
ISLVAL
ISEN
CINV
PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 (see page 1153)
GLOBALSYNC3 GLOBALSYNC2 GLOBALSYNC1 GLOBALSYNC0
PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 (see page 1154)
SYNC3 SYNC2 SYNC1 SYNC0
PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 (see page 1156)
PWM7EN PWM6EN PWM5EN PWM4EN PWM3EN PWM2EN PWM1EN PWM0EN
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 (see page 1158)
PWM7INV PWM6INV PWM5INV PWM4INV PWM3INV PWM2INV PWM1INV PWM0INV
PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 (see page 1160)
PWMRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 1162)
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 (see page 1165)
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 (see page 1168)
FAULT7 FAULT6 FAULT5 FAULT4 FAULT3 FAULT2 FAULT1 FAULT0
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
PWMFAULTVAL, type R/W, offset 0x024, reset 0x0000.0000 (see page 1170)
FAULT3 FAULT2 FAULT1 FAULT0
PWMENUPD, type R/W, offset 0x028, reset 0x0000.0000 (see page 1172)
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
ENUPD7
ENUPD6
ENUPD5
ENUPD4
PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 (see page 1176)
DBFALLUPD
DBRISEUPD
DBCTLUPD
GENBUPD
PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 (see page 1176)
DBFALLUPD
DBRISEUPD
DBCTLUPD
GENBUPD
PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 (see page 1176)
DBFALLUPD
DBRISEUPD
DBCTLUPD
GENBUPD
ENUPD3
ENUPD2
ENUPD1
ENUPD0
GENAUPD
LATCH MINFLTPER FLTSRC
CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE
GENAUPD
LATCH MINFLTPER FLTSRC
CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE
GENAUPD
LATCH MINFLTPER FLTSRC
CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE
1390
Texas Instruments-Production Data
January 22, 2012