TMS320C6412AZNZ5 Datasheet, PDF (136/163 Pages) Texas Instruments – TMS320C6412 Fixed-Point Digital Signal Processor

Peripheral Component Interconnect (PCI) Timing
NO.
4
t_su(IV-PCLKH)
5
t_h(IV-PCLKH)
Table 14−3. Timing Requirements for PCI Inputs (see Figure 14−3)
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
−500
33 MHz
MIN MAX
7
0
−600
−720
66 MHz
MIN MAX
3
0
UNIT
ns
ns
PCLK
4
5
PCI Input
Inputs Valid
Figure 14−3. PCI Input Timing (33-/66-MHz)
Table 14−4. Switching Characteristics Over Recommended Operating Conditions for PCI Outputs
(see Figure 14−4)
NO.
1
t_d(PCLKH-OV)
2
t_d(PCLKH-OLZ)
3
t_d(PCLKH-OHZ)
PARAMETER
Delay time, PCLK high to output valid
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
−500
33 MHz
MIN MAX
2
11
2
28
−600
−720
66 MHz
MIN MAX
2
6
2
14
UNIT
ns
ns
ns
PCLK
PCI Output
1
1
2
3
Figure 14−4. PCI Output Timing (33-/66-MHz)
136 SPRS219J
April 2003 − Revised October 2010