TMS320C6743 Datasheet, PDF (133/153 Pages) Texas Instruments – TMS320C6743 Fixed/Floating-Point Digital Signal Processor

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LPSC NUMBER
25
26
27-31
TMS320C6743
SPRS565B – APRIL 2009 – REVISED JUNE 2011
Table 5-79. PSC1 Default Module Configuration (continued)
MODULE NAME
SCR7
(Br 12)
SCR12
(Br 18)
—
POWER DOMAIN
AlwaysON (PD0)
AlwaysON (PD0)
—
DEFAULT MODULE
STATE
Enable
Enable
—
AUTO SLEEP/WAKE
ONLY
Yes
Yes
—
5.24.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In the device, for both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
5.24.2.2 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 5-80.
MODULE STATE MODULE RESET
Enable
De-asserted
Disable
De-asserted
SyncReset
SwRstDisable
Asserted
Asserted
Auto Sleep
De-asserted
Auto Wake
De-asserted
Table 5-80. Module States
MODULE
CLOCK
On
Off
On
Off
Off
Off
MODULE STATE DEFINITION
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The device is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
Copyright © 2009–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 133
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