TMS320C6743 Datasheet, PDF (1/153 Pages) Texas Instruments – TMS320C6743 Fixed/Floating-Point Digital Signal Processor

TMS320C6743
www.ti.com
SPRS565B – APRIL 2009 – REVISED JUNE 2011
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Check for Samples: TMS320C6743
1 TMS320C6743 Fixed/Floating-Point Digital Signal Processor
1.1 Features
12
• Highlights
– Up to 375-MHz FIxed/Floating-Point VLIW
DSP Core
– Enhanced Direct-Memory-Access Controller
(EDMA3)
– Two External Memory Interfaces
– Two Configurable 16550 type UART Modules
– One Serial Peripheral Interface (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
– Two Master/Slave Inter-Integrated Circuit
Modules (I2C)
– RMII Ethernet Media Access COntroller
(EMAC)
– Three Event Capture (eCAP) Modules
– Two Quadrature Encoding (eQEP) Modules
– Two Multi-Channel Audio Serial Ports
(McASP)
– Programmable Real-Time Unit Subsystem
(PRUSS)
– Two 64-bit Timers (each configurable as
32-bit)
• Applications
– Industrial Control
– Networking
– High-Speed Encoding
– Professional Audio™
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• TMS320C674x Floating Point VLIW DSP Core
– Load-Store Architecture With Non-Aligned
Support
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
• C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 3000/2250 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 128K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• 3.3V LVCMOS IOs
• Two External Memory Interfaces:
– EMIFA
• NOR (8-Bit-Wide Data)
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
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