LM3S9BN6 Datasheet, PDF (1309/1381 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex

Stellaris^® LM3S9BN6 Microcontroller
Figure 26-20. ADC Input Equivalency Diagram
VDD
ESD
Clamp
R_ADC
V_IN
ESD
Clamp
I_L
Stellaris® Microcontroller
10-bit
converter
C_ADC
Sample and hold
ADC converter
Table 26-23. ADC Module External Reference Characteristics^a
Parameter Parameter Name
Min
Nom
Max
Unit
V_REFA
External voltage reference for ADC^b
2.97
-
3.03
V
I_L
External voltage reference leakage current
-
-
2.0
µA
a. Care must be taken to supply a reference voltage of acceptable quality.
b. Ground is always used as the reference level for the minimum conversion value.
Table 26-24. ADC Module Internal Reference Characteristics
Parameter
V_REFI
Parameter Name
Internal voltage reference for ADC
Min
Nom
-
3.0
Max
Unit
-
V
26.14 Synchronous Serial Interface (SSI)
Table 26-25. SSI Characteristics
Parameter
No.
Parameter Parameter Name
Min Nom Max
Unit
S1
T_{CLK_PER}
SSIClk cycle time^a
40
-
-
ns
S2
T_{CLK_HIGH}
SSIClk high time
-
0.5
-
t clk_per
S3
T_{CLK_LOW}
SSIClk low time
S4
T_CLKRF
SSIClk rise/fall time^b
-
0.5
-
-
4
6
t clk_per
ns
S5
T_DMD
Data from master valid delay time
0
-
1
system clocks
S6
T_DMS
Data from master setup time
1
-
-
system clocks
S7
T_DMH
Data from master hold time
2
-
-
system clocks
S8
T_DSS
Data from slave setup time
1
-
-
system clocks
S9
T_DSH
Data from slave hold time
2
-
-
system clocks
a. In master mode, the system clock must be at least twice as fast as the SSIClk; in slave mode, the system clock must be
at least 12 times faster than the SSIClk.
b. Note that the delays shown are using 8-mA drive strength.
January 21, 2012
Texas Instruments-Production Data
1309