LM3S9BN6 Datasheet, PDF (1052/1381 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex

Universal Serial Bus (USB) Controller
OTG A / Host Mode
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1)
Base 0x4005.0000
Offset 0x117
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE
DT
reserved
Type R/W
R/W
R/W
RO
R/W
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
Name
AUTOCL
Type
R/W
Reset
0
Description
Auto Clear
Value Description
0 No effect.
1 Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 966.
6
AUTORQ
R/W
0
Auto Request
Value Description
0 No effect.
1 Enables the REQPKT bit to be automatically set when the RXRDY
bit is cleared.
Note: This bit is automatically cleared when a short packet is
received.
5
DMAEN
R/W
0
DMA Request Enable
Value Description
0 Disables the µDMA request for the receive endpoint.
1 Enables the µDMA request for the receive endpoint.
Note:
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
4
PIDERR
RO
0
PID Error
Value Description
0 No error.
1 Indicates a PID error in the received packet of an isochronous
transaction.
This bit is ignored in bulk or interrupt transactions.
1052
Texas Instruments-Production Data
January 21, 2012