RM44L920_16 Datasheet, PDF (130/162 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
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7.11.2 I2C I/O Timing Specifications
Table 7-31. I2C Signals (SDA and SCL) Switching Characteristics⁽¹⁾
PARAMETER
STANDARD MODE
MIN
MAX
FAST MODE
MIN
MAX
UNIT
t_c(I2CCLK)
Cycle time, internal module clock for I2C,
prescaled from VCLK
75.2
149
75.2
149
ns
f_(SCL)
t_c(SCL)
t_{su(SCLH-SDAL)}
SCL clock frequency
Cycle time, SCL
Setup time, SCL high before SDA low (for a
repeated START condition)
0
100
10
4.7
0
400
kHz
2.5
µs
0.6
µs
t_h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated
START condition)
4
0.6
µs
t_w(SCLL)
t_w(SCLH)
t_su(SDA-SCLH)
t_h(SDA-SCLL)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (for I2C-bus
devices)
4.7
1.3
4
0.6
250
100
0
3.45 ⁽²⁾
0
µs
µs
ns
0.9
µs
t_w(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
1.3
µs
t_{su(SCLH-SDAH)}
Setup time, SCL high before SDA high (for STOP
condition)
4.0
0.6
µs
t_w(SP)
C_b ⁽³⁾
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50
ns
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum t_h(SDA-SCLL) for I2C-bus devices has only to be met if the device does not stretch the low period (t_w(SCLL)) of the SCL
signal.
(3) C_b = The total capacitance of one bus line in pF.
SDA
SCL
Stop
t_w(SDAH)
t_w(SCLL)
t_r(SCL)
t_w(SCLH)
t_su(SDA-SCLH)
t_w(SP)
t_{su(SCLH-SDAH)}
Start
t_c(SCL)
t_h(SCLL-SDAL)
t_f(SCL)
t_h(SDA-SCLL)
t_h(SCLL-SDAL)
t_{su(SCLH-SDAL)}
Repeated Start
Figure 7-19. I2C Timings
Stop
130 Peripheral Information and Electrical Specifications
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