TMS470R1A384_15 Datasheet, PDF (13/63 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

TMS470R1A384
www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
TERMINAL
NAME
PZ PGE
CLKOUT
PORRST
57 81
85 118
RST
86 121
AWD
TCK
TDI
TDO
TEST
TMS
TMS2
TRST
25 36
54 76
52 74
53 75
87 124
11 17
10 16
100 144
Table 2. Terminal Functions (continued)
INPUT
VOLTAGE ^{(1) (2)}
OUTPUT
CURRENT ⁽³⁾
INTERNAL
PULLUP/
PULLDOWN
DESCRIPTION
SYSTEM MODULE (SYS)
3.3 V
4 mA
Bidirectional clock out. CLKOUT can be
programmed as a GIO pin or the output of
SYSCLK, ICLK, or MCLK.
3.3 V
IPD (20 µA)
Input master chip power-up reset. External V_CC
monitor circuitry must assert a power-on reset.
3.3 V
4 mA
IPU (20 µA)
Bidirectional reset. The internal circuitry can
assert a reset, and an external system reset can
assert a device reset.
On this pin, the output buffer is implemented as
an open drain (drives low only).
To ensure an external reset is not arbitrarily
generated, TI recommends that an external
pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
3.3 V
4 mA
Analog watchdog reset. The AWD pin provides
a system reset if the WD KEY is not written in
time by the system, providing an external RC
network circuit is connected. If the user is not
using AWD, TI recommends that this pin be
connected to ground or pulled down to ground
by an external resistor.
For more details on the external RC network
circuit, see the TMS470R1x System Module
Reference Guide (literature number SPNU189).
TEST/DEBUG (T/D)
2 mA
IPD (20 µA)
Test clock. TCK controls the test hardware
(JTAG).
2 mA
Test data in. TDI inputs serial data to the test
IPU (20 µA) instruction register, test data register, and
programmable test address (JTAG).
4 mA
IPD (20 µA)
Test data out. TDO outputs serial data from the
test instruction register, test data register,
identification register, and programmable test
address (JTAG).
3.3 V
IPD (20 µA)
Test enable. Reserved for internal use only. TI
recommends that this pin be connected to
ground or pulled down to ground by an external
resistor.
2 mA
IPU (20 µA)
Serial input for controlling the state of the CPU
test access port (TAP) controller (JTAG).
2 mA
IPU (20 µA)
IPD (20 µA)
Serial input for controlling the second TAP. TI
recommends that this pin be connected to V_CCIO
or pulled up to V_CCIO by an external resistor.
Test hardware reset to TAP1 and TAP2.
IEEE Std 1149.1 (JTAG) Boundary-Scan Logic.
TI recommends that this pin be pulled down to
ground by an external resistor.
Copyright © 2005–2008, Texas Instruments Incorporated
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