LP38851S-ADJ Datasheet, PDF (13/29 Pages) Texas Instruments – LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start

www.ti.com
LP38851
SNVS492C – JUNE 2007 – REVISED APRIL 2013
Figure 30. F_ZERO and F_POLE vs Gain
SETTING THE OUTPUT VOLTAGE
(Refer to TYPICAL APPLICATION CIRCUIT)
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
V_OUT
=
V_ADJ
x
§
¨¹⁺
©
§
¨
©
R1
R2
¹·¸_¹·¨
(5)
The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of V_ADJ is specified, the use of low quality
resistors for R1 and R2 can easily produce a V_OUT value that is unacceptable.
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F_Z pole set by R1 and
C_FF.
( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ
(6)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for C_FF, for a range of V_OUT values. Other values of R1, R2, and C_FF are available that will give
similar results.
V_OUT
0.8V
0.9V
1.00V
1.1V
1.2V
1.3V
1.4V
1.5V
1.6V
1.7V
1.8V
R1
1.07 kΩ
1.50 kΩ
1.00 kΩ
1.65 kΩ
1.40 kΩ
1.15 kΩ
1.07 kΩ
2.00 kΩ
1.65 kΩ
2.55 kΩ
2.94 kΩ
Table 1.
R2
1.78 kΩ
1.87 kΩ
1.00 kΩ
1.37 kΩ
1.00 kΩ
715 Ω
590 Ω
1.00 kΩ
750 Ω
1.07 kΩ
1.13 kΩ
C_FF
220 pF
180 pF
270 pF
150 pF
180 pF
220 pF
220 pF
120pF
150 pF
100 pF
82 pF
F_Z
676 kHz
589 kHz
589 kHz
643 kHz
631 kHz
629 kHz
676 kHz
663 kHz
643 kHz
624 kHz
660 kHz
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP38851
Submit Documentation Feedback
13