LP38851S-ADJ Datasheet, PDF (12/29 Pages) Texas Instruments – LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start

LP38851
SNVS492C – JUNE 2007 – REVISED APRIL 2013
APPLICATION INFORMATION
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EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in TYPICAL APPLICATION
CIRCUIT.
Output Capacitor
A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can
be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and
returned to the device ground pin with a clean analog ground.
Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide
sufficient capacitance over temperature.
Tantalum capacitors will also provide stable operation across the entire operating temperature range. However,
the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum
recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or
Aluminum, to be added in parallel.
Input Capacitor
The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended.
Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor
(the lower, the better).
Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at
cold temperatures. They are not recommended for any application where the ambient temperature falls below
0°C.
Bias Capacitor
The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is
recommended).
Feed Forward Capacitor, C_FF
(Refer to TYPICAL APPLICATION CIRCUIT)
When using a ceramic capacitor for C_OUT, the typical ESR value will be too small to provide any meaningful
positive phase compensation, F_Z, to offset the internal negative phase shifts in the gain loop.
F_Z = 1 / (2 x π x C_OUT x ESR)
(1)
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient
response of the device. This capacitor, C_FF, in parallel with R1, will form a zero in the loop response given by the
formula:
F_Z = 1 / (2 x π x C_FF x R1)
(2)
For optimum load transient response select C_FF so the zero frequency, F_Z, falls between 500 kHz and 750 kHz.
C_FF = 1 / (2 x π x R1 x F_Z)
(3)
The phase lead provided by C_FF diminishes as the DC gain approaches unity, or V_OUT approaches V_ADJ. This is
because C_FF also forms a pole with a frequency of:
F_P = 1 / (2 x π x C_FF x (R1 || R2) )
(4)
It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far
apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The
phase lead provided from C_FF diminishes quickly as the output voltage is reduced, and has no effect when V_OUT
= V_ADJ. For this reason, relying on this compensation technique alone is adequate only for higher output
voltages. For the LP38851, the practical minimum V_OUT is 0.8V when a ceramic capacitor is used for C_OUT.
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