LM3S1751 Datasheet, PDF (13/694 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1439 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Revision History .................................................................................................. 24
Documentation Conventions ................................................................................ 31
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 56
Processor Register Map ....................................................................................... 57
PSR Register Combinations ................................................................................. 62
Memory Map ....................................................................................................... 70
Memory Access Behavior ..................................................................................... 72
SRAM Memory Bit-Banding Regions .................................................................... 74
Peripheral Memory Bit-Banding Regions ............................................................... 75
Exception Types .................................................................................................. 80
Interrupts ............................................................................................................ 81
Exception Return Behavior ................................................................................... 86
Faults ................................................................................................................. 87
Fault Status and Fault Address Registers .............................................................. 88
Cortex-M3 Instruction Summary ........................................................................... 90
Core Peripheral Register Regions ......................................................................... 93
Memory Attributes Summary ................................................................................ 96
TEX, S, C, and B Bit Field Encoding ..................................................................... 99
Cache Policy for Memory Attribute Encoding ....................................................... 100
AP Bit Field Encoding ........................................................................................ 100
Memory Region Attributes for Stellaris Microcontrollers ........................................ 100
Peripherals Register Map ................................................................................... 101
Interrupt Priority Levels ...................................................................................... 126
Example SIZE Field Values ................................................................................ 154
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 158
JTAG_SWD_SWO Signals (108BGA) ................................................................. 159
JTAG Port Pins Reset State ............................................................................... 159
JTAG Instruction Register Commands ................................................................. 166
System Control & Clocks Signals (100LQFP) ...................................................... 170
System Control & Clocks Signals (108BGA) ........................................................ 170
Reset Sources ................................................................................................... 171
Clock Source Options ........................................................................................ 176
Possible System Clock Frequencies Using the SYSDIV Field ............................... 179
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 179
System Control Register Map ............................................................................. 183
RCC2 Fields that Override RCC fields ................................................................. 198
Hibernate Signals (100LQFP) ............................................................................. 234
Hibernate Signals (108BGA) .............................................................................. 235
Hibernation Module Register Map ....................................................................... 241
Flash Protection Policy Combinations ................................................................. 255
User-Programmable Flash Memory Resident Registers ....................................... 258
Flash Register Map ............................................................................................ 258
GPIO Pins With Non-Zero Reset Values .............................................................. 281
GPIO Pins and Alternate Functions (100LQFP) ................................................... 281
GPIO Pins and Alternate Functions (108BGA) ..................................................... 282
GPIO Signals (100LQFP) ................................................................................... 283
June 18, 2012
13
Texas Instruments-Production Data