DS90LV048A_16 Datasheet, PDF (13/22 Pages) Texas Instruments – 3-V LVDS Quad CMOS Differential Line Receiver

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DS90LV048A
SNLS045C – JULY 1999 – REVISED JULY 2016
Typical Application (continued)
0 V) gives a DNM of a comfortable 60 mV. With the standard threshold region of ±100 mV, the external fail-safe
biasing would need to be +25 mV with respect to +100 mV or +125 mV, giving a DNM of 160 mV which is
stronger fail-safe biasing than is necessary for the DS90LV048A. If more DNM is required, then a stronger fail-
safe bias point can be set by changing resistor values.
Figure 20. VTC of the DS90LV048A LVDS Receiver
9.2.3 Application Curve
Figure 21. Power Supply Current vs Frequency
10 Power Supply Recommendations
Although the DS90LV047A draws very little power while at rest, its overall power consumption increases due to a
dynamic current component. The DS90LV048A power supply connection must take this additional current
consumption into consideration for maximum power requirements.
11 Layout
11.1 Layout Guidelines
• Use at least 4 PCB layers (top to bottom): LVDS signals, ground, power, and TTL signals.
• Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. Best practice is to
put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
• Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
11.1.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high-frequency ceramic (surface mount is recommended)
0.1-μF and 0.001-μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple
vias must be used to connect the decoupling capacitors to the power planes. A 10-μF (35-V) or greater solid
tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply
and ground.
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