DRV8302 Datasheet, PDF (13/21 Pages) Texas Instruments – Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator – Hardware Controlled

DRV8302
www.ti.com
SLES267 – AUGUST 2011
The buck has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than
92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the
pin to transition high when a pull-up resistor is used.
The buck minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good
comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from turning
on until the output voltage is lower than 107%.
The SS_TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS_TR pin is
discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature
fault,
The buck, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit.
The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage
once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup
and overcurrent fault conditions to help control the inductor current.
PROTECTION FEATURES
Power Stage Protection
The DRV8302 provides over-current and under-voltage protection for the MOSFET power stage. During fault
shut down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.
Over-Current Protection (OCP) and Reporting
To protect the power stage from damage due to high currents, a V_DS sensing circuitry is implemented in the
DRV8302. Based on R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be
calculated which, when exceeded, triggers the OC protection feature. This voltage threshold level is
programmable through the OC_ADJ terminal (see next section) by applying an external reference voltage with a
DAC or resistor divider from DVDD.
There are a total of 2 OC_MODE settings selectable with the M_OC pin.
1. Current Limit Mode (M_OC = LOW)
When current limit mode is enabled, device operates current limiting instead of OC shut down during OC
event. During OC event, the FET that detected OC will turn off until next PWM cycle. The over-current event
is reported through OCTW pin. OCTW reporting should hold low during same PWM cycle or for a max 64µs
period (internal timer) so external controller has enough time to sample the warning signal. If in the middle of
reporting, other FET(s) gets OC, then OCTW reporting will hold low and recount another 64µS unless PWM
cycles on both FETs are ended.
2. OC latch shut down mode (M_OC = HIGH)
When OC occurs, device will turn off both high side and low side FETs in the same phase if any of the FETs
in that phase has OC.
OC_ADJ
When external MOSFET is turned on, the output current flows through the on resistance, RD_S(on) of the
MOSFET, which creates a voltage drop V_DS. The over current protection event will be enabled when the V_DS
exceeds a pre-set value. The voltage on OC_ADJ pin will be used to pre-set the OC tripped value. The OC
tripped value I_OC has to meet following equations:
R2
(R1 + R2) ^{´ DVDD = VDS}
(2)
I_OC
=
V_DS
R_{DS(on )}
(3)
Where
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Product Folder Link(s): DRV8302
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