CDCP1803_13 Datasheet, PDF (13/25 Pages) Texas Instruments – 1:3 LVPECL CLOCK BUFFER

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CDCP1803
SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013
APPLICATION INFORMATION
LVPECL RECEIVER INPUT TERMINATION
The input of the CDCP1803 has a high impedance and comes with a large common-mode voltage range.
For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line). If a
differential signal drives the CDCP1803, then a 100-Ω termination resistor is recommended to be placed as close
as possible across the input terminals. An even better approach is to install 2 × 50-Ω resistors, with the center
tap connected to a capacitor (C) to terminate odd-mode noise and make up for transmission line mismatches.
The VBB output can also be connected to the center tap to bias the input signal to (V_DD – 1.3 V) (see Figure 9).
LVPECL
50 Ω
150 Ω
C_AC
50 Ω
CDCP1803
IN
50 Ω
150 Ω
C_AC
50 Ω
C
IN
VBB
S0085-02
Figure 9. Recommended AC-Coupling LVPECL Receiver Input Termination
LVPECL
50 Ω
130 Ω
83 Ω
CDCP1803
IN
50 Ω
130 Ω
IN
83 Ω
S0086-02
Figure 10. Recommended DC-Coupling LVPECL Receiver Input Termination
The CDCP1803 can also be driven by single-ended signals. Typically, the input signal becomes connected to
one input, while the complementary input must be properly biased to the center voltage of the incoming input
signal. For LVCMOS signals, this would be V_CC/2, realized by a simple voltage divider (e.g., two 10-kΩ resistors).
The best option (especially if the dc offset of the input signal might vary) is to ac-couple the input signal and then
rebias the signal using the VBB reference output. See Figure 11.
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