BQ27530-G1 Datasheet, PDF (13/20 Pages) Texas Instruments – Battery Management Unit Impedance Track Fuel Gauge for Use With the bq2416x Charger Controller

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COMMUNICATIONS
bq27530-G1
SLUSAL5 – DECEMBER 2012
I²C INTERFACE
The bq27530-G1 supports the standard I²C read, incremental read, quick read, one byte write, and incremental
write functions. The 7 bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as
1010101. The first 8-bits of the I²C protocol will; therefore, be 0xAA or 0xAB for write or read, respectively.
Host generated
Gauge generated
S ADDR[6:0] 0 A CMD [7:0] A DATA [7:0] A P
S ADDR[6:0] 1 A DATA [7:0]
(a) 1-byte write
(b) quick read
S ADDR[6:0] 0 A CMD [7:0] A Sr ADDR[6:0] 1 A DATA [7:0] N P
(c) 1- byte read
NP
S ADDR[6:0] 0 A
CMD [7:0]
A Sr ADDR[6:0] 1 A
(d) incremental read
DATA [7:0]
A ...
DATA [7:0]
NP
S ADDR[6:0] 0 A CMD[7:0] A DATA [7:0] A DATA [7:0]
(e) incremental write
(S = Start , Sr = Repeated Start , A = Acknowledge , N = No Acknowledge , and P = Stop).
A ... A P
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I²C communication engine, will increment whenever data is acknowledged by the bq27530-G1 or
the I²C master. “Quick writes” function in the same manner and are a convenient means of sending multiple
bytes to consecutive command locations (such as two-byte commands that require two bytes of data)
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x6B (NACK command):
I²C Time Out
The I²C engine will release both SDA and SCL if the I²C bus is held low for 2 seconds. If the bq27530-G1 was
holding the lines, releasing them will free them for the master to drive the lines. If an external condition is holding
either of the lines low, the I²C engine will enter the low power sleep mode.
Copyright © 2012, Texas Instruments Incorporated
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