BQ2011_15 Datasheet, PDF (13/26 Pages) Texas Instruments – Gas Gauge IC for High Discharge Rates

bq2011
The gas gauge display and the gas gauge portion of the
TMPGG register are adjusted for cold temperature de-
pendencies. A piece-wise correction is performed as fol-
lows:
Temperature
> 0°C
-20°C < T < 0°C
< -20°C
Available Capacity Calculation
NAC / “Full Reference”
0.75 _* NAC / “Full Reference”
0.5 _* NAC / “Full Reference”
The adjustment between > 0°C and -20°C < T < 0°C has a
4°C hysteresis.
Nominal Available Charge Register (NAC)
The read/write NACH register (address=03h) and the
read-only NACL register (address=17h) are the main
gas gauging registers for the bq2011. The NAC registers
are incremented during charge actions and decremented
during discharge and self-discharge actions. The correc-
tion factors for charge/discharge efficiency are applied
automatically to NAC.
On reset, the NACH and NACL registers are cleared to
zero. NACL stops counting when NACH reaches zero.
When the bq2011 detects a valid charge, NACL resets to
zero; writing to the NAC register affects the available
charge counts and, therefore, affects the bq2011 gas
gauge operation.
Battery Identification Register (BATID)
The read/write BATID register (address=04h) is avail-
able for use by the system to determine the type of bat-
tery pack. The BATID contents are retained as long as
VCC is greater than 2V. The contents of BATID have no
effect on the operation of the bq2011. There is no de-
fault setting for this register.
Last Measured Discharge Register (LMD)
LMD is a read/write register (address=05h) that the
bq2011 uses as a measured full reference. The bq2011
adjusts LMD based on the measured discharge capacity
of the battery from full to empty. In this way the bq2011
updates the capacity of the battery. LMD is set to PFC
during a bq2011 reset.
Secondary Status Flags Register (FLGS2)
The read-only FLGS2 register (address=06h) contains
the secondary bq2011 flags.
The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
charge action is initiated. The CR flag remains asserted
if the charge rate does not fall below 2 counts/sec.
The CR values are:
FLGS2 Bits
7
65
4
3
2
1
0
CR - -
-
-
-
-
-
Where CR is:
0 When charge rate falls below 2 counts/sec
1 When charge rate is above 2 counts/sec
The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac-
tors are used. The time to change CR varies due to the
user-selectable count rates.
The discharge rate flags, DR2–0, are bits 6–4.
FLGS2 Bits
7
6
5
4
3210
-
DR2 DR1 DR0 - - -
They are used to determine the present discharge re-
gime as follows:
DR2
0
0
0
0
1
DR1
0
0
1
1
0
DR0
0
1
0
1
0
VSR (V)
VSR < 50mV
50mV < VSR < 100mV
(overload, OVLD=1)
100mV < VSR < 150mV
150mV < VSR < 253mV
VSRD > 253mV
The overload flag (OVLD) is asserted when a discharge
overload is detected, VSRD > 50mV. OVLD remains as-
serted as long as the condition persists and is cleared
when VSRD < 50mV.
FLGS2 Bits
7
65
4
3
2
-
--
-
-
-
1
0
- OVLD
DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to VSS. The rate at which
this measurement is made varies with device activity.
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