TMS320C6454BZTZ8 Datasheet, PDF (122/232 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
SPRS311I – APRIL 2006 – REVISED MARCH 2012
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NOTE
The POR pin should be held inactive (high) throughout the Warm Reset sequence.
Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met.
The RESET pin should not be tied together with the POR pin.
7.6.3 System Reset
The emulator initiates a System Reset via the ICEPick module. This ICEPick-initiated reset is non-
maskable. To invoke the maximum reset via the ICEPick module, the user can perform the following from
the Code Composer Studio™ menu: Debug → Advanced Resets → System Reset.
The following memory contents are maintained during a System Reset:
• DDR2 Memory Controller: The DDR2 Memory Controller registers are not reset. In addition, the DDR2
SDRAM memory content is retained if the user places the DDR2 SDRAM in self-refresh mode before
invoking the System Reset.
• EMIFA: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are
not reset.
Test, emulation, and clock logic are unaffected. The device configuration pins are also not re-latched and
the state of the peripherals (see Table 3-4) is not affected.
During a System Reset, the following happens:
1. The System Reset is initiated by the emulator.
During this time, the following happens:
– The reset signals flow to the entire chip resetting all the modules on chip except the test and
emulation logic.
– The PLL controllers are not reset. Internal system clocks are unaffected. If PLL1/PLL2 were locked
before the System Reset, they remain locked.
– The RESETSTAT pin goes low to indicate an internal reset is being generated.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the
PLL controllers pause their system clocks for about 10 cycles.
At this point:
– The state of the peripherals before the System Reset is not changed. For example, if McBSP0 was
in the enabled state before System Reset, it will remain in the enabled state after System Reset.
– The I/O pins are controlled as dictated by the DEVSTAT register.
– The DDR2 Memory Controller and EMIFA registers retain their previous values. Only the DDR2
Memory Controller and EMIFA state machines are reset by the System Reset.
– The PLL controllers are operating in the mode prior to System Reset. System clocks are
unaffected.
The boot sequence is started after the system clocks are restarted. Since the configuration pins (including
the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as shown in the
DEVSTAT register, are used to select the boot mode.
7.6.4 CPU Reset
A CPU Reset is initiated by the HPI or PCI peripheral. This reset only affects the CPU. During a PCI-
initiated CPU Reset, the PCI pins are set to their reset state. With the exception of the HRDY/PIRDY pin,
the PCI pins have a reset state of high-impedance; the HRDY/PIRDY pin goes high during reset.
7.6.5 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority
reset request. The rest request priorities are as follows (high to low):
• Power-on Reset
122 C64x+ Peripheral Information and Electrical Specifications
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