TMS320C6454BZTZ8 Datasheet, PDF (121/232 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
www.ti.com
SPRS311I – APRIL 2006 – REVISED MARCH 2012
When the POR pin is deasserted, the configuration pin values are latched and the PLL controllers
change their system clocks to their default divide-down values. PLL2 is taken out of reset and
automatically starts its locking sequence. Other device initialization is also started.
4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,
PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of
both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their
respective system reference clocks. After the pause the system clocks are restarted at their default
divide-by settings.
5. The device is now out of reset, device execution begins as dictated by the selected boot mode (see
Section 2.4, Boot Sequence).
NOTE
To most of the device, reset is de-asserted only when the POR and RESET pins are both
de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is
held low past the low period of the POR pin, most of the device will remain in reset. The only
exception being that PLL2 is taken out of reset as soon as POR is de-asserted (driven high),
regardless of the state of the RESET pin. The RESET pin should not be tied together with
the POR pin.
7.6.2 Warm Reset (RESET Pin)
A Warm Reset has the same effects as a Power-on Reset, except that in this case, the test and emulation
logic and PLL2 are not reset.
The following sequence must be followed during a Warm Reset:
1. Hold the RESET pin low for a minimum of 24 CLKIN1 cycles. Within the minimum 24 CLKIN1 cycles.
Within the low period of the RESET pin, the following happens:
– The Z group pins, low group pins, and the high group pins are set to their reset state with one
exception:
The PCI pins are not affected by warm reset if the PCI module was enabled before RESET went
low. In this case, PCI pins stay at whatever their value was before RESET went low.
– The reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules
that use reset asynchronously.
– The PLL1 controller is reset thereby switching back to bypass mode and resetting all its registers to
their default values. PLL1 is placed in reset and loses lock. The PLL1 controller clocks start running
at the frequency of the system reference clock. The clocks are propagated throughout the chip to
reset modules that use reset synchronously.
– The PLL2 controller is reset thereby resetting all its registers to their default values. The PLL2
controller clocks start running at the frequency of the system reference clock. PLL2 is not reset,
therefore it remains locked.
– The RESETSTAT pin becomes active (low), indicating the device is in reset.
2. The RESET pin may now be released (driven inactive high).
When the RESET pin is released, the configuration pin values are latched and the PLL controllers
immediately change their system clocks to their default divide-down values. Other device initialization
is also started.
3. After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are
allowed to finish their current cycles and then paused for 10 cycles of their respective system reference
clocks. After the pause the system clocks are restarted at their default divide-by settings.
4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see
Section 2.4, Boot Sequence).
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C64x+ Peripheral Information and Electrical Specifications 121
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