LM3S9DN5_15 Datasheet, PDF (1205/1391 Pages) Texas Instruments – Stellaris LM3S9DN5 Microcontroller

Stellaris^® LM3S9DN5 Microcontroller
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the
interrupt controller if the corresponding bit in this register is set.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
INTERROR INTDIR INTTIMER INTINDEX
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
INTERROR
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Phase Error Interrupt Enable
Value Description
1 An interrupt is sent to the interrupt controller when the
INTERROR bit in the QEIRIS register is set.
0 The INTERROR interrupt is suppressed and not sent to the
interrupt controller.
2
INTDIR
R/W
0
Direction Change Interrupt Enable
Value Description
1 An interrupt is sent to the interrupt controller when the INTDIR
bit in the QEIRIS register is set.
0 The INTDIR interrupt is suppressed and not sent to the interrupt
controller.
1
INTTIMER
R/W
0
Timer Expires Interrupt Enable
Value Description
1 An interrupt is sent to the interrupt controller when the
INTTIMER bit in the QEIRIS register is set.
0 The INTTIMER interrupt is suppressed and not sent to the
interrupt controller.
July 03, 2014
Texas Instruments-Production Data
1205