TLC5923_16 Datasheet, PDF (12/28 Pages) Texas Instruments – 16-CHANNEL LED DRIVER WITH DOT CORRECTION

TLC5923
SLVS550B – DECEMBER 2004 – REVISED JANUARY 2013
LED
Good
Good
Bad
Bad
Table 4. LOD Data Truth Table
ON/OFF
On
Off
On
Off
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LOD BIT
0
0
1
0
Key Timing Requirements to Reading LOD
• LOD status flag
The LOD status flag becomes active if the output voltage is <0.3 V (typical) when the output sink current turns
on. There is a 1-µs time delay from the time the output sink current turns on until the time the LOD status flag
becomes valid. The timing for each channel’s LOD status to become valid is shifted by the 30 ns channel-to-
channel turn-on time. After BLANK goes low, OUT0 LOD status is valid when tpd2 + tpd4 = 60 ns + 1 µs =
1.06 µs. OUT1 LOD status is valid when tpd2 + tpd4 + td = 60 ns + 1 µs + 30 ns = 1.09 µs. OUT3 LOD status
is valid when tpd2 + tpd4 + 2*td = 1.12 µs, and so on.
• LOD internal latch
The TLC5923 has an internal latch to hold each channel’s LOD status flag information, as shown in
Figure 11. When MODE is low, the LOD status information is latched into this latch on the rising edge of
XLAT. This is an edge-triggered latch. To ensure that a valid LOD status flag is latched, BLANK must be low
when XLAT goes high. After the rising edge of XLAT, changes in the status flags do not affect the values in
the LOD latch.
• Loading LOD data to the input shift register
The LOD data must be transferred to the input shift register before it is available to be clocked out of SOUT.
The internal shift register has a set/reset function that is controlled by the LOD internal latch. While XLAT is
high, the LOD internal latch holds the input shift register in either set or reset, depending on the value in the
latch. This effectively puts the LOD data into the input shift register where it remains as long as XLAT is high.
The values in the input shift register are unaffected by any other signals, including SIN and SCLK while XLAT
is high. During this time, the status of OUT15 is present on SOUT.
• Latching LOD data into the internal shift register
While XLAT is high, the status of OUT15 is present on SOUT. When XLAT transitions low, all data is latched
into the Input shift register, and the LOD internal latch is disconnected from the internal shift register.
• Clocking LOD data out of SOUT
While XLAT is low and SCLK is low, the status of OUT15 is on SOUT. On the next rising edge of SCLK, the
status of OUT14 shifts to SOUT. Each subsequent rising edge of SCLK shifts the LOD data out of SOUT.
XLAT must stay low until all LOD data is clocked out of SOUT. See Shifting the LOD Data Out section for
more details.
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