PCI2050APDV Datasheet, PDF (12/17 Pages) Texas Instruments – Two 32-Bit, 66-MHz PCI Buses

PCI2050A
PCI-to-PCI BRIDGE
SCPS067 – MAY 2001
bridge configuration header (continued)
status register
The bit 5 in status register is hardwired to 0 in PCI2050. However, in PCI2050A it indicates whether the primary
PCI interface is 66-MHz capable or not.
Bit
15
14
13
12
11 10 9 8
7
6
5
4
3
2
1
0
Name
Status
Type R/W R/W R/W R/W R/W R R R/W R R
R
R
R
R
R
R
Default
0
0
0
0
0
01 0
1
0
0
1
0
0
0
0
Register:
Type:
Offset:
Default:
Status
Read-only, read/write (see individual bit descriptions)
06h
0290h
Table 2. Status Register
BIT
15-6
5
4-0
TYPE
Same as
PCI2050
R
Same as
PCI2050
FUNCTION
Same as PCI2050.
66-MHz capable. Bit 5 indicates whether the primary interface is 66 MHz capable. It reads as 0 when CONFIG66 is tied
low to indicate that PCI2050A is not 66-MHz capable and reads as 1 when CONFIG66 is tied high to indicate that the
primary bus is 66-MHz capable.
Same as PCI2050.
revision ID register
The revision ID register indicates the silicon version of PCI2050A.
Bit
7
6
5
4
3
2
1
0
Name
Revision ID
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
1
Register:
Type:
Offset:
Default:
Revision ID
Read-only
08h
01h
12
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