PCI2050APDV Datasheet, PDF (1/17 Pages) Texas Instruments – Two 32-Bit, 66-MHz PCI Buses

PCI2050A
PCI-to-PCI BRIDGE
D Two 32-Bit, 66-MHz PCI Buses
D Configurable for PCI Power Management
Interface Specification
D Provides CompactPCI Hot-Swap
Functionality
D 3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments
D Provides Internal Two-Tier Arbitration for
up to Nine Secondary Bus Masters and
Supports an External Secondary Bus
Arbiter
D Burst Data Transfers With Pipeline
Architecture to Maximize Data Throughput
in Both Directions
D Independent Read and Write Buffers for
Each Direction
SCPS067 – MAY 2001
D Up to Three Delayed Transactions in Both
Directions
D Provides 10 Secondary PCI Clock Outputs
D Predictable Latency per PCI Local Bus
Specification
D Propagates Bus Locking
D Supports Write Combining for Enhanced
Data Throughput
D Supports Frame-to-Frame Delay of Only
Four PCI Clocks From One Bus to Another
D Secondary Bus is Driven Low During Reset
D Provides VGA/Palette Memory and I/O, and
Subtractive Decoding Options
D Advanced Submicron, Low-Power CMOS
Technology
D Packaged in 208-Terminal QFP
description
This data sheet for PCI2050A lists only enhancements to PCI2050 and must be used in conjunction with
PCI2050, PCI-to-PCI bridge, data manual (Literature number SCPS053A)
The Texas Instruments PCI2050A PCI-to-PCI bridge provides a high performance connection path between two
peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz.
Transactions occur between masters on one and targets on another PCI bus, and the PCI2050A allows bridged
transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data
throughput, and the two bus traffic paths through the bridge act independently.
The PCI2050A bridge is compliant with the PCI local bus specification, and can be used to overcome the
electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical
buses. The PCI2050A provides two-tier internal arbitration for up to nine secondary bus masters and may be
implemented with an external bus arbiter.
The CompactPCI hot-swap extended PCI capability makes the PCI2050A an ideal solution for multifunction
compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050A bridge is compliant with PCI-to-PCI bridge specification 1.1. The PCI2050A provides compliance
for PCI Power Management 1.0 and 1.1. The PCI2050A has been designed to lead the industry in power
consumption and data throughput. An advanced CMOS process achieves low system power consumption while
operating at PCI clock rates up to 66-MHz.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CompactPCI is a trademark of PICMG-PCI Industrial Computer Manufacturers Group, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2001, Texas Instruments Incorporated
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