LMH6714 Datasheet, PDF (12/30 Pages) National Semiconductor (TI) – Wideband Video Op Amp; Single, Single with Shutdown and Quad

LMH6714, LMH6720
LMH6722, LMH6722-Q1
SNOSA39G – NOVEMBER 2002 – REVISED APRIL 2013
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Disabled, the LMH6720 inputs and output become high impedances. While disabled the LMH6720 quiescent
current is approximately 500μA. Because of the pull up resistor on the disable circuit the I_CC and I_EE currents are
not balanced in the disabled state. The positive supply current (I_CC) is approximately 500μA while the negative
supply current (I_EE) is only 200μA. The remaining I_EE current of 300μA flows through the disable pin.
The disable function can be used to create analog switches or multiplexers. Implement a single analog switch
with one LMH6720 positioned between an input and output. Create an analog multiplexer with several
LMH6720's. The LMH6720 is at it's best at a gain of 1 for multiplexer applications because there is no R_G to
shunt signals to ground.
DISABLE LIMITATIONS (LMH6720 ONLY)
The feedback Resistor (R_F) limits off isolation in inverting gain configurations. During shutdown the impedance of
the LMH6720 inputs and output become very high (>1MΩ), however R_F and R_G are the dominant factor for
effective output impedance.
Do not apply voltages greater than +V_CC or less than 0V (V_CC/2 single supply) to the disable pin. The input ESD
diodes will also conduct if the signal leakage through the feedback resistors brings the inverting input near either
supply rail.
+5V
C4
C2
.01PF
IN
6.8PF
+
R_IN
50:
-
.1PF
C1
50: ^OUT
R_OUT
300:
R_F
300:
R_G
C3
.01PF
6.8PF
C5
-5V
Figure 35. Typical Application with Suggested Supply Bypassing
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. The following Evaluation boards
are available with sample parts:
LMH6714
LMH6720
LMH6722
SOT-23
SOIC
SOT-23
SOIC
SOIC
TSSOP
LMH730216
LMH730227
LMH730216
LMH730227
LMH730231
LMH730131
To reduce parasitic capacitances, the ground plane should be removed near the input and output pins. To
reduce series inductance, trace lengths of components in the feedback loop should be minimized. For long signal
paths controlled impedance lines should be used, along with impedance matching at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to
ground are applied in pairs. The larger electrolytic bypass capacitors can be located anywhere on the board, the
smaller ceramic capacitors should be placed as close to the device as possible. In addition Figure 35 shows a
capacitor (C1) across the supplies with no connection to ground. This capacitor is optional, however it is required
for best 2nd Harmonic suppression. If this capacitor is omitted C2 and C3 should be increased to .1μF each.
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