LM5071MT-50-NOPB Datasheet, PDF (12/24 Pages) Texas Instruments – LM5071 Power Over Ethernet PD Controller with Auxiliary Power Interface

LM5071
SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013
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Classification
To classify the PD, the PSE will present a voltage between 14.5V and 20.5V to the PD. The LM5071 enables
classification mode at a nominal input voltage of 11.5V. An internal 1.5V linear regulator and an external resistor
connected to the RCLASS pin provide classification programming current. Table 1 shows the external
classification resistor required for a particular class.
The classification current flows through the IC into the classification resistor. The suggested resistor values take
into account the bias current flowing into the IC. A different desired RCLASS can be calculated by dividing 1.5V
by the desired classification current.
Per the IEEE 802.3af specification, classification is optional, and the PSE will default to class 0 if a valid
classification current is not detected. If PD classification is not desired (i.e., Class 0), simply leave the RCLASS
pin open. The classification time period may not last longer than 75ms as per IEEE 802.3af. The LM5071 will
remain in classification mode until V_IN is greater than 25V.
Class
0
1
2
3
4
Table 2. Classification Levels and Required External Resistors
PMIN
0.44W
0.44W
3.84W
6.49W
Reserved
PMAX
12.95W
3.84W
6.49W
12.95W
Reserved
ICLASS
(MIN)
0mA
9mA
17mA
26mA
36mA
ICLASS
(MAX)
4mA
12mA
20mA
30mA
44mA
RCLASS
Open
150Ω
82.5Ω
54.9Ω
38.3Ω
Undervoltage Lockout (UVLO)
The IEEE 802.3af specification states that the PSE will supply power to the PD within 400ms after completion of
detection. The LM5071 contains a programmable line Under Voltage Lock Out (UVLO) circuit. The first resistor
should be connected between the V_IN to UVLO pins; the bottom resistor in the divider should be connected
between the UVLO and UVLORTN pins.
The divider must be designed such that the voltage at the UVLO pin equals 2.0V when V_IN reaches the desired
minimum operating level. If the UVLO threshold is not met, the interface control and SMPS control will remain in
standby.
UVLO hysteresis is accomplished with an internal 10uA current source that is switched on and off into the
impedance of the UVLO set point divider. When the UVLO threshold is exceeded, the current source is activated
to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.00V threshold, the
current source is turned off, causing the voltage at the UVLO pin to fall. The LM5071 UVLO thresholds cannot be
programmed lower than 25V, the AUX pin should be used to force UVLO release below 25V.
There are many additional uses for the UVLO pin. The UVLO function can also be used to implement a remote
enable / disable function. Pulling the UVLO pin down below the UVLO threshold disables the interface and SMPS
controller unless forced on via AUX pin operation.
AUX Pin Operation
The AUX pin can be used to force operation (UVLO release) of the interface and switching regulator at any input
voltage above 9.5V. This is especially useful for auxiliary input (wall transformer) input voltages. The pin has a
2.5V threshold (0.5V hysteresis) and an input impedance of approximately 350kΩ. The input resistor provides a
defined pull down impedance if the pin is left open by the user. An external pull down resistor should be used to
provide additional noise immunity. The resultant pin voltage from the external resistor divider should be well
above the 2.5V threshold to ensure proper auxiliary operation. See Figure 14 for an example of a simple yet
robust auxiliary configuration.
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