DRV8801-Q1 Datasheet, PDF (12/23 Pages) Texas Instruments – DMOS FULL-BRIDGE MOTOR DRIVERS

DRV8800-Q1
DRV8801-Q1
SLVSAS7 – FEBRUARY 2011
www.ti.com
Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF
ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run
the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition,
the outputs of the device are disabled.
Shutdown
As a measure to protect the device, faults caused by very high junction temperatures or low voltage on VCP
disable the outputs of the device until the fault condition is removed. At power on, the UVLO circuit disables the
drivers.
Low-Power Mode
Control input nSLEEP is used to minimize power consumption when the DRV8800-Q1/DRV8801-Q1 is not in
use. This disables much of the internal circuitry, including the internal voltage rails and charge pump. nSLEEP is
asserted low. A logic high on this input pin results in normal operation. When switching from low to high, the user
should allow a 1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize.
• MODE 1 (MODE on the DRV8800-Q1)
Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device
in slow-decay mode.
• MODE 2 (DRV8801-Q1 only)
MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay
recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has
current recirculation through the high-side drivers. A logic low has current recirculation through the low-side
drivers.
Braking
The braking function is implemented by driving the device in slow-decay mode (MODE 1 pin is high) and
deasserting the enable to low. Because it is possible to drive current in both directions through the DMOS
switches, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode
is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the
maximum ratings of the device are not exceeded in worse-case braking situations – high-speed and high-inertia
loads.
Diagnostic Output
The nFAULT pin signals a problem with the chip via an open-drain output. A motor fault, undervoltage condition,
or T_J > 160°C drives the pin active low. This output is not valid when nSLEEP puts the device into minimum
power dissipation mode (i.e., nSLEEP is low). nFAULT stays asserted (nFAULT = L) until VBB reaches VBBNFR
to give the charge pump headroom to reach its undervoltage threshold. nFAULT is a status-only signal and does
not affect any device functionality. The H-bridge portion still operates normally down to VBB = 8 V with nFAULT
asserted.
Thermal Shutdown (TSD)
Two die-temperature monitors are integrated on the chip. As die temperature increases toward the maximum, a
thermal warning signal is triggered at 160°C. This fault drives the nFAULT low, but does not disable the
operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs are
disabled until the internal temperature falls below a hysteresis of 15°C.
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