DRV8801-Q1 Datasheet, PDF (11/23 Pages) Texas Instruments – DMOS FULL-BRIDGE MOTOR DRIVERS

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VOUT+
VOUT- ^High-Z
DRV8800-Q1
DRV8801-Q1
SLVSAS7 – FEBRUARY 2011
IPEAK
IOUTx
IOCP
Enable,
Source
or Sink
BLANK
Charge Pump
Counter
NFAULT
tBLANK
tOCP
Motor Lead
Short Condition
Figure 2. Overcurrent Control Timing
Normal DC
Motor Capacitance
FUNCTIONAL DESCRIPTION
Device Operation
The DRV8800-Q1/DRV8801-Q1 is designed to drive one dc motor. The current through the output full-bridge
switches and all N-channel DMOS are regulated with a fixed off-time PWM control circuit.
Logic Inputs
It is recommended to use a high-value pullup resistor when logic inputs are pulled up to V_DD. This resistor limits
the current to the input in case an overvoltage event occurs. Logic inputs are nSLEEP, MODE, PHASE, and
ENABLE. Voltages higher than 7 V on any logic input can cause damage to the input structure.
VREG (DRV8800-Q1 Only)
This output represents a measurement of the internal regulator voltage. This pin should be left disconnected. A
voltage of approximately 7.5 V can be measured at this pin.
VPROPI (DRV8801-Q1 Only)
This output offers an analog voltage proportional to the winding current. Voltage at this terminal is five times
greater than the motor winding current (VPROPI = 5×I). VPROPI is meaningful only if there is a resistor
connected to the SENSE pin. If SENSE is connected to ground, VPROPI measures 0 V. During slow decay,
VPROPI outputs 0 V. VPROPI can output a maximum of 2.5 V, since at 500 mV on SENSE, the H-bridge is
disabled.
© 2011, Texas Instruments Incorporated
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Product Folder Link(s): DRV8800-Q1 DRV8801-Q1