DRV3203E-Q1 Datasheet, PDF (12/39 Pages) Texas Instruments – Three-Phase Brushless Motor Driver

DRV3203E-Q1
SLVSCE5A – NOVEMBER 2013 – REVISED JANUARY 2014
www.ti.com
FE_MTOC
MTOC
FE_VCCOC
VCCOC
FE_VCCOV
VCCOV
FE_VDDOV
VDDOV
FE_CPOV
CPOV
FE_CPUV
CPUV
FE_VBOV
VBOV
FE_VBUV
VBUV
FE_TSD
TSD
Figure 6. FAULT Pin Enable Logic
FAULT
SDNEN0 (address 0x06): Pre-Driver Shutdown Enable Register 0
Bit Name
Type
7
SE_MTOC RW
6
SE_VCCOC RW
5
SE_VCCOV RW
4
SE_VDDOV RW
3
SE_CPOV RW
2
SE_CPUV RW
1
SE_VBOV RW
0
SE_VBUV RW
Reset
1
1
1
1
1
1
1
1
Description
Pre-driver shutdown enable of FLTFLG0 register bits
0: Disabling of the pre-driver outputs does not occur when the fault flag bit is 1.
1: Disabling of the pre-driver outputs occurs when the fault flag bit is 1. Both the high-side
and low-side FETs turn off.
See Figure 7.
SDNEN1 (address 0x07): Pre-Driver Shutdown Enable Register 1
Bit Name
7:1 RSVD
0
SE_TSD
Type
R
RW
Reset
0000 000
1
Description
Reserved
Pre-driver shutdown enable of TSD flag bits
0: Disabling of the pre-driver outputs does not occur when the TSD flag bit is 1.
1: Disabling of the pre-driver outputs occurs when the TSD flag bit is 1. Both the high-side and
low-side FETs turn off.
See Figure 7.
12
Submit Documentation Feedback
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: DRV3203E-Q1