CDCLVP1216 Datasheet, PDF (12/22 Pages) Texas Instruments – 16 LVPECL Output, High-Performance Clock Buffer

CDCLVP1216
SCAS877C – MAY 2009 – REVISED AUGUST 2011
Figure 13 illustrates this recommended power-supply decoupling method.
Board
V_CC
Supply
Ferrite Bead
Chip
Supply
C
10 mF
C
1 mF
C
0.1 mF (x6)
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Figure 13. Power-Supply Decoupling
LVPECL Output Termination
The CDCLVP1216 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are
required to ensure correct operation of the device and to minimize signal integrity. The proper termination for
LVPECL outputs is a 50 Ω to (V_CC –2) V, but this dc voltage is not readily available on PCB. Therefore, a
Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled
configurations. These configurations are shown in Figure 14a and b for V_CC = 2.5 V and Figure 15a and b for V_CC
= 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the
receiver end. If the supply voltage for the driver and receiver is different, ac coupling is required.
CDCLVP1216
VCC
VCC
250 W
250 W
LVPECL
62.5 W
62.5 W
(a) Output DC Termination
CDCLVP1216
VBB
LVPECL
86 W
86 W
50 W
50 W
(b) Output AC Termination
Figure 14. LVPECL Output DC and AC Termination for V_CC = 2.5 V
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