CDCLVP1216 Datasheet, PDF (1/22 Pages) Texas Instruments – 16 LVPECL Output, High-Performance Clock Buffer

CDCLVP1216
www.ti.com
SCAS877C – MAY 2009 – REVISED AUGUST 2011
16 LVPECL Output,
High-Performance Clock Buffer
Check for Samples: CDCLVP1216
FEATURES
1
•2 2:16 Differential Buffer
• Selectable Clock Inputs Through Control Pin
• Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
• 16 LVPECL Outputs
• Maximum Clock Frequency: 2 GHz
• Maximum Core Current Consumption: 110 mA
• Very Low Additive Jitter: <100 fs,rms in 10-kHz
to 20-MHz Offset Range
• 2.375 V to 3.6 V Device Power Supply
• Maximum Propagation Delay: 550 ps
• Maximum Output Skew: 30 ps
• LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
• Industrial Temperature Range: –40°C to +85°C
• ESD Protection Exceeds 2 kV (HBM)
• Available in 7-mm × 7-mm QFN-48 (RGZ)
Package
APPLICATIONS
• Wireless Communications
• Telecommunications/Networking
• Medical Imaging
• Test and Measurement Equipment
DESCRIPTION
The CDCLVP1216 is a highly versatile, low additive
jitter buffer that can generate 16 copies of LVPECL
clock outputs from one of two selectable LVPECL,
LVDS, or LVCMOS inputs for a variety of
communication applications. It has a maximum clock
frequency up to 2 GHz. The CDCLVP1216 features
an on-chip multiplexer (MUX) for selecting one of two
inputs that can be easily configured solely through a
control pin. The overall additive jitter performance is
less than 0.1 ps, RMS from 10 kHz to 20 MHz, and
overall output skew is as low as 30 ps, making the
device a perfect choice for use in demanding
applications.
The CDCLVP1216 clock buffer distributes one of two
selectable clock inputs (IN0, IN1) to 16 pairs of
differential LVPECL clock outputs (OUT0, OUT15)
with minimum skew for clock distribution. The
CDCLVP1216 can accept two clock sources into an
input multiplexer. The inputs can be LVPECL, LVDS,
or LVCMOS/LVTTL.
The CDCLVP1216 is specifically designed for driving
50-Ω transmission lines. When driving the inputs in
single-ended mode, the LVPECL bias voltage
(V_{AC_REF}) should be applied to the unused negative
input pin. However, for high-speed performance up to
2 GHz, differential mode is strongly recommended.
The CDCLVP1216 is packaged in a small 48-pin,
7-mm x 7-mm QFN package and is characterized for
operation from –40°C to +85°C.
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
INP0
INN0
INP1
INN1
LVPECL
OUTP[15...0]
16
OUTN[15...0]
16
IN_SEL
V_{AC_REF}
Reference
Generator
GND
GND
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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