TMS570LS0714 Datasheet, PDF (113/159 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS0714
SPNS226D – JUNE 2013 – REVISED SEPTEMBER 2015
7.5.3 ADC Electrical and Timing Specifications
Table 7-23. MibADC Recommended Operating Conditions
AD_REFHI
AD_REFLO
V_AI
I_AIC
PARAMETER
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Analog input voltage
Analog input clamp current⁽²⁾
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
MIN
AD_REFLO
V_SSAD ⁽¹⁾
AD_REFLO
–2
MAX
V_CCAD ⁽¹⁾
AD_REFHI
AD_REFHI
2
(1) For V_CCAD and V_SSAD recommended operating conditions, see Table Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
UNIT
V
V
V
mA
Table 7-24. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions
R_mux
R_samp
C_mux
C_samp
I_AIL
I_AIL
I_AOSB1 ⁽¹⁾
I_AOSB2 ⁽¹⁾
I_AOSB1 ⁽¹⁾
I_AOSB2 ⁽¹⁾
I_ADREFHI
I_CCAD
PARAMETER
Analog input mux on-resistance
ADC sample switch on-resistance
Input mux capacitance
ADC sample capacitance
Analog off-state input leakage current
Analog off-state input leakage current
ADC1 Analog on-state input bias current
ADC2 Analog on-state input bias current
ADC1 Analog on-state input bias current
ADC2 Analog on-state input bias current
AD_REFHI input current
Static supply current
DESCRIPTION/CONDITIONS
See Figure 7-11
See Figure 7-11
See Figure 7-11
See Figure 7-11
V_CCAD = 3.6 V
maximum
V_SSAD ≤ V_IN < V_SSAD + 100mV
V_SSAD + 100mV ≤ V_IN ≤ V_CCAD – 200mV
V_CCAD – 200mV < V_IN ≤ V_CCAD
V_CCAD = 5.25 V
maximum
V_SSAD ≤ V_IN < V_SSAD + 300mV
V_SSAD + 300mV ≤ V_IN ≤ V_CCAD – 300mV
V_CCAD – 300mV < V_IN ≤ V_CCAD
V_CCAD = 3.6 V
maximum
V_SSAD ≤ V_IN < V_SSAD + 100mV
V_SSAD + 100mV < V_IN < V_CCAD – 200mV
V_CCAD – 200mV < V_IN < V_CCAD
V_CCAD = 3.6 V
maximum
V_SSAD ≤ V_IN < V_SSAD + 100mV
V_SSAD + 100mV ≤ V_IN ≤ V_CCAD – 200mV
V_CCAD - 200mV < V_IN ≤ V_CCAD
V_CCAD = 5.25 V
maximum
V_SSAD ≤ V_IN < V_SSAD + 300mV
V_SSAD + 300mV ≤ V_IN ≤ V_CCAD – 300mV
V_CCAD – 300mV < V_IN ≤ V_CCAD
V_CCAD = 5.25 V
maximum
V_SSAD ≤ V_IN < V_SSAD + 300mV
V_SSAD + 300mV ≤ V_IN ≤ V_CCAD – 300mV
V_CCAD – 300mV < V_IN ≤ V_CCAD
AD_REFHI = V_CCAD, AD_REFLO = V_SSAD
Normal operating mode
ADC core in power down mode
MIN TYP
–300
–200
–200
–1000
–250
–250
–8
–4
–4
–7
–4
–4
–10
–5
–5
–8
–5
–5
MAX
250
250
16
13
200
200
500
250
250
1000
2
2
12
2
2
10
3
3
14
3
3
12
3
15
5
UNIT
Ω
Ω
pF
pF
nA
nA
nA
nA
nA
nA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
µA
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to I_AOSB1 + I_AOSB2.
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Peripheral Information and Electrical Specifications 113
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