ADC31RF80 Datasheet, PDF (113/136 Pages) Texas Instruments – 3-GSPS Telecom Receiver and Feedback Device

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8.5.11 Power Detector Page
8.5.11.1 Register 000h (address = 000h), Power Detector Page
ADC31RF80
SBAS860 – AUGUST 2017
7
0
W-0h
6
0
W-0h
Bit Field
7-1 0
0
PKDET EN
Figure 224. Register 000h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
PKDET EN
R/W-0h
Table 108. Register 000h Field Descriptions
Type
W
R/W
Reset
0h
0h
Description
Must write 0
This bit enables the peak power and crossing detector.
0 = Power detector disabled
1 = Power detector enabled
8.5.11.2 Register 001h-002h (address = 001h-002h), Power Detector Page
Figure 225. Register 001h
7
6
5
4
3
2
1
0
BLKPKDET [7:0]
R/W-0h
Figure 226. Register 002h
7
6
5
4
3
2
1
0
BLKPKDET [15:8]
R/W-0h
Bit Field
7-0 BLKPKDET
Table 109. Register 001h-002h Field Descriptions
Type
R/W
Reset
0h
Description
This register specifies the block length in terms of number of
samples (S`) used for peak power computation. Each sample S`
is a peak of 8 actual ADC samples. This parameter is a 17-bit
value directly in linear scale. In decimation mode, the block
length must be a multiple of a divide-by-4 or -6 complex: length
= 5 × decimation factor.
The divide-by-8 to -32 complex: length = 10 × decimation factor.
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