TMS320F28069_17 Datasheet, PDF (112/177 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016
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6.9.6.1 McBSP Electrical Data/Timing
6.9.6.1.1 McBSP Transmit and Receive Timing
Table 6-42. McBSP Timing Requirements⁽¹⁾⁽²⁾
NO.
M11
M12
M13
M14
t_c(CKRX)
t_w(CKRX)
t_r(CKRX)
t_f(CKRX)
M15 t_su(FRH-CKRL)
M16 t_h(CKRL-FRH)
M17 t_su(DRV-CKRL)
M18 t_h(CKRL-DRV)
M19 t_su(FXH-CKXL)
M20 t_h(CKXL-FXH)
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
Fall time, CLKR/X
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
MIN
1
50 ⁽⁴⁾
2P
P–7
18
2
0
6
18
2
0
6
18
2
0
6
MAX
20 ^{(3) (4)}
1
7
7
UNIT
kHz
MHz
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (20 MHz).
(4) Maximum McBSP module clock frequency decreases to 10 MHz for internal CLKR.
112 Detailed Description
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