TLC5945_16 Datasheet, PDF (11/30 Pages) Texas Instruments – 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

TLC5945
www.ti.com
PRINCIPLES OF OPERATION
SLVS755 – MARCH 2007
SERIAL INTERFACE
The TLC5945 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK
signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of
XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of
XLAT signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending
on the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle.
Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the
grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the
existing grayscale data. Figure 6 shows the timing chart. More than two TLC5945s can be connected in series
by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5945s is shown in Figure 7. The SOUT pin can also be connected to the controller to receive status
information from TLC5945 as shown in Figure 16.
MODE
DC Data Input Mode
th3
tsu3
XLAT
SIN
DC
MSB
SCLK ¹
DC
LSB
th2
96
1st GS Data Input Cycle
GS1
MSB
tsu2
1
SOUT
-
DC
-
-
MSB
BLANK
GSCLK
tpd4
tpd1
OUT0
(current)
OUT1
(current)
GS Data Input Mode
twh2
GS1
LSB
tsu1
192
GS1
MSB
2nd GS Data Input Cycle
GS2
MSB
th1
twh0
193
1
GS2
LSB
192
twl0
SID1 SID1
MSB MSB-1
SID1 GS2
LSB MSB
GS3
MSB
tsu0
th0
193
1
tpd0
SID2 SID2
MSB MSB-1
twh3
1st GS Data Output Cycle
tsu5
1
tpd3
tpd3
th4
4096
Tgsclk
2nd GS Data Output Cycle
tsu4
twh1
1
twl1
tpd3
touton
OUT15
(current)
XERR
tpd2
Figure 6. Serial Data Input Timing Chart
SIN(a )
SIN
SOUT
TLC5945 (a)
SIN
SOUT
TLC5945 (b)
SCLK, XLAT,
BLANK,
GSCLK,
MODE
Figure 7. Cascading Two TLC5945 Devices
SOUT(b )
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