TLC5540_14 Datasheet, PDF (11/24 Pages) Texas Instruments – 8-Bit Resolution Differential Linearity Error Integral Linearity Error

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TLC5540
SLAS105D − JANUARY 1995 − REVISED APRIL 2004
PRINCIPLES OF OPERATION
functional description
The TLC5540 uses a modified semiflash architecture as shown in the functional block diagram. The four most
significant bits (MSBs) of every output conversion result are produced by the upper comparator block CB1. The
four least significant bits (LSBs) of each alternate output conversion result are produced by the lower
comparator blocks CB-A and CB-B in turn (see Figure 12).
The reference voltage that is applied to the lower comparator resistor string is one sixteenth of the amplitude
of the refence applied to the upper comparator resistor string. The sampling comparators of the lower
comparator block require more time to sample the lower voltages of the reference and residual input voltage.
By applying the residual input voltage to alternate lower comparator blocks, each comparator block has twice
as much time to sample and convert as would be the case if only one lower comparator block were used.
VI(1)
VI(2)
VI(3)
VI(4)
ANALOG IN
(Sampling Points)
CLK (Clock)
Upper Comparators Block (CB1)
Upper Data
Lower Reference Voltage
CLK1
CLK2
CLK3
CLK4
S(1) C(1) S(2) C(2) S(3) C(3) S(4) C(4)
UD(0)
UD(1)
UD(2)
UD(3)
RV(0)
RV(1)
RV(2)
RV(3)
Lower Comparators Block (CB-A)
Lower Data (A)
S(1)
H(1)
C(1) S(3)
LD(−1)
H(3)
C(3)
LD(1)
Lower Comparators Block (CB-B) ^H(0)
C(0) S(2)
H(2)
C(2) S(4)
H(4)
Lower Data (B)
tpd
D1 −D8 (Data Output)
LD(−2)
OUT(−2)
LD(0)
OUT(−1)
OUT(0)
LD(2)
OUT(1)
Figure 12. Internal Functional Timing Diagram
This conversion scheme, which reduces the required sampling comparators by 30 percent compared to
standard semiflash architectures, achieves significantly higher sample rates than the conventional semiflash
conversion method.
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