THMC10_08 Datasheet, PDF (11/22 Pages) Texas Instruments – REMOTE/LOCAL TEMPERATURE MONITOR WITH SMBus INTERFACE

THMC10
REMOTE/LOCAL TEMPERATURE MONITOR
WITH SMBus INTERFACE
SLIS089 − DECEMBER 1999
PRINCIPLES OF OPERATION
standby input (STBY) (continued)
Forcing the STBY terminal low activates the hardware standby mode. In a notebook computer, this line may
be connected to the system suspend-state signal. Pulling the STBY terminal low overrides any software
acquisition command. If a hardware or software standby command is received while an acquisition is in
progress, the acquisition cycle is truncated, and the data from that acquisition is not latched into either
temperature reading register. The previous data is not changed and remains available.
Peak supply current drain during an auto-aquire period is typically 300 µA. Slowing down the auto-acquire rate
minimizes the average supply current (see A/D and supply dc electrical characteristics). In between
acquisitions, the instantaneous supply current is about 40 µA, due to the current consumed by the auto-aquire
rate timer. In standby mode, supply current drops to about 3 µA. At very low supply voltages (under the
power-on-reset threshold), the supply current is higher due to the address terminal bias currents. It can be as
high as 100 µA, depending on ADD0 and ADD1 settings.
under/overtemperature and remote diode diagnostics interrupt alert terminal (ALERT)
The THMC10 allows the user to program upper and lower temperature limits for both the on-chip and the remote
temperature sensor. If any of these limits are exceeded, or an open external diode is detected, the THMC10
asserts the ALERT to a logic low state to alert the user that an interrupt has occurred. This feature is useful in
applications where minimal SMBus traffic is desired by only interrogating the THMC10 for faults or temperature
when a fault has occurred.
It is recommended that the user always double-check the validity of an ALERT condition by reading the current
temperature values and comparing them with the programmed high and low temperature limits.
The ALERT function can also be masked by setting bit 6 in the configuration register to a logic 1. If this bit is
set, the ALERT terminal is not asserted low, even if a trip point is reached.
The ALERT signal and corresponding status register bits can only be cleared by reading from the alert response
address (0001 100) or by a power-on reset of the device (see alert response address section).
NOTE:
The ALERT terminal is an open-drain output and requires an external pullup resistor.
alert response address (0001 100)
The SMBus alert response address allows the user to quickly check the status of the ALERT terminal via the
SMBus receive byte protocol (see Figure 5). This is useful in applications where another device on the SMBus
needs to know the status of the THMC10 ALERT terminal without requiring the complex logic needed to decode
the contents of the status register. If the ALERT has been asserted low, the data read from the alert response
address is the THMC10 slave address (determined by ADD0 and ADD1 – see Table 8). If the fault condition
which caused the ALERT to go low is no longer present when the alert response address is successfully read,
the ALERT terminal returns to a logic high state and the corresponding bits in the THMC10 status register are
cleared. If the ALERT terminal has not been asserted low, the THMC10 responds to the alert response address
with a NACK signal after the alert response address is sent.
The alert response address can activate several different slave devices simultaneously. It is similar to the
general call address outlined in the I²C Bus specification. If more than one device attempts to respond to the
alert response address, SMBus arbitration rules apply, causing the device with the lowest slave address to win
control of the SMBus. The device that loses arbitration in this example does not generate an ACK signal and
continues to hold the ALERT terminal low until the device with the losing slave address is serviced. This
technique requires the SMBus host controller to use level-sensitive interrupt inputs in order to assure that each
device is serviced.
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