SM74104 Datasheet, PDF (11/16 Pages) Texas Instruments – SM74104 High Voltage Half-Bridge Gate Driver with Adaptive Delay

Operational Description
ADAPTIVE SHOOT-THROUGH PROTECTION
SM74104 is a high voltage, high speed dual output driver de-
signed to drive top and bottom MOSFET’s connected in syn-
chronous buck or half-bridge configuration, from one exter-
nally provided PWM signal. SM74104 features adaptive delay
to prevent shoot-through current through top and bottom
MOSFETs during switching transitions. Referring to the tim-
ing diagram Figure 1, the rising edge of the PWM input (IN)
turns off the bottom MOSFET (LO) after a short propagation
delay (t_P). An adaptive circuit in the SM74104 monitors the
bottom gate voltage (LO) and triggers a programmable delay
generator when the LO pin falls below an internally set thresh-
old (≈ Vdd/2). The gate drive of the upper MOSFET (HO) is
disabled until the deadtime expires. The upper gate is en-
abled after the TIMER delay (t_P+T_RT) , and the upper MOS-
FET turns-on. The additional delay of the timer prevents lower
and upper MOSFETs from conducting simultaneously, there-
by preventing shoot-through.
A falling transition on the PWM signal (IN) initiates the turn-
off of the upper MOSFET and turn-on of the lower MOSFET.
A short propagation delay (t_P) is encountered before the up-
per gate voltage begins to fall. Again, the adaptive shoot-
through circuitry and the programmable deadtime TIMER
delays the lower gate turn-on time. The upper MOSFET gate
voltage is monitored and the deadtime delay generator is trig-
gered when the upper MOSFET gate voltage with respect to
ground drops below an internally set threshold (≈ Vdd/2). The
lower gate drive is momentarily disabled by the timer and
turns on the lower MOSFET after the deadtime delay expires
(t_P+T_RT).
The RT pin is biased at 3V and current limited to 1mA. It is
designed to accommodate a resistor between 5K and 100K,
resulting in an effective dead-time proportional to RT and
ranging from 90ns to 200ns. RT values below 5K will saturate
the timer and are not recommended.
Startup and UVLO
Both top and bottom drivers include under-voltage lockout
(UVLO) protection circuitry which monitors the supply voltage
(V_DD) and bootstrap capacitor voltage (V_HB – V_HS) indepen-
dently. The UVLO circuit inhibits each driver until sufficient
supply voltage is available to turn-on the external MOSFETs,
and the built-in hysteresis prevents chattering during supply
voltage transitions. When the supply voltage is applied to
V_DD pin of SM74104, the top and bottom gates are held low
until V_DD exceeds UVLO threshold, typically about 6.9V. Any
UVLO condition on the bootstrap capacitor will disable only
the high side output (HO).
LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1. A low ESR/ESL capacitor must be connected close to the
IC, and between V_DD and V_SS pins and between HB and
HS pins to support high peak currents being drawn from
V_DD during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (V_SS).
3. In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
4. Grounding considerations:
a) The first priority in designing grounding connections is
to confine the high peak currents from charging and
discharging the MOSFET gate in a minimal physical
area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the
MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
b) The second high current path includes the bootstrap
capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body
diode. The bootstrap capacitor is recharged on the cycle-
by-cycle basis through the bootstrap diode from the
ground referenced V_DD bypass capacitor. The recharging
occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the
circuit board is important to ensure reliable operation.
5. The resistor on the RT pin must be placed very close to
the IC and seperated from high current paths to avoid
noise coupling to the time delay generator which could
disrupt timer operation.
POWER DISSIPATION CONSIDERATIONS
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are related to the switching frequency (f), output load capac-
itance on LO and HO (C_L), and supply voltage (V_DD) and can
be roughly calculated as:
P_DGATES = 2 • f • C_L • V_DD2
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO out-
puts. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the out-
put loads and agrees well with the above equation. This plot
can be used to approximate the power losses due to the gate
drivers.
Gate Driver Power Dissipation (LO + HO)
V_CC = 12V, Neglecting Diode Losses
30160006
The bootstrap diode power loss is the sum of the forward bias
power loss that occurs while charging the bootstrap capacitor
and the reverse bias power loss that occurs during reverse
recovery. Since each of these events happens once per cycle,
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