LP38511TJ-ADJ Datasheet, PDF (11/21 Pages) Texas Instruments – LP38511-ADJ 800mA Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator

LP38511-ADJ
www.ti.com
SNVS545D – JANUARY 2009 – REVISED APRIL 2013
Please refer to Application Note AN-1378 Method For Calculating Output Voltage Tolerances in Adjustable
Regulators SNVA112 for additional information on how resistor tolerances affect the calculated V_OUT value.
ENABLE OPERATION
The Enable ON threshold is typically 1.2V, and the OFF threshold is typically 1.0V. To ensure reliable operation
the Enable pin voltage must rise above the maximum V_EN(ON) threshold and must fall below the minimum V_EN(OFF)
threshold. The Enable threshold has typically 200 mV of hysteresis to improve noise immunity.
The Enable pin (EN) has no internal pull-up or pull-down to establish a default condition and, as a result, this pin
must be terminated either actively or passively.
If the Enable pin is driven from a single ended device (such as the collector of a discrete transistor) a pull-up
resistor to V_IN, or a pull-down resistor to ground, will be required for proper operation. A 1 kΩ to 100 kΩ resistor
can be used as the pull-up or pull-down resistor to establish default condition for the EN pin. The resistor value
selected should be appropriate to swamp out any leakage in the external single ended device, as well as any
stray capacitance.
If the Enable pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator
output), the pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin should be connected directly to the adjacent V_IN
pin.
POWER DISSIPATION/HEAT-SINKING
A heat-sink may be required depending on the maximum power dissipation (P_D(MAX)), maximum ambient
temperature (T_A(MAX))of the application, and the thermal resistance (θ_JA) of the package. Under all possible
conditions, the junction temperature (T_J) must be within the range specified in the Operating Ratings. The total
power dissipation of the device is given by:
P_D = ( (V_IN−V_OUT) x I_OUT) + ((V_IN) x I_GND)
(7)
where I_GND is the operating ground current of the device (specified under Electrical Characteristics).
The maximum allowable junction temperature rise (ΔT_J) depends on the maximum expected ambient
temperature (T_A(MAX)) of the application, and the maximum allowable junction temperature (T_J(MAX)):
ΔT_J = T_J(MAX) − T_A(MAX)
(8)
The maximum allowable value for junction to ambient Thermal Resistance, θ_JA, can be calculated using the
formula:
θ_JA = ΔT_J / P_D(MAX)
(9)
LP38511-ADJ is available in PFM and SO PowerPad surface mount packages. For a comparison of the PFM
package to the standard TO-263 package see Application Note AN-1797 PFM Package (SNVA328). The thermal
resistance depends on amount of copper area, or heat sink, and on air flow. See Application Note AN-1520 A
Guide to Board Layout for Best Thermal Resistance for Exposed Packages (SNVA183) for guidelines.
Heat-Sinking the PFM Package
The DAP of the PFM package is soldered to the copper plane for heat sinking. The PFM package has a θ_JA
rating of 67°C/W, and a θ_JC rating of 2°C/W. The θ_JA rating of 67°C/W includes the device DAP soldered to an
area of 0.055 square inches (0.22 in x 0.25 in) of 1 ounce copper on a two sided PCB, with no airflow. See
JEDEC standard EIA/JESD51-3 for more information.
Figure 21 shows a curve for the θ_JA of PFM package for different thermal via counts under the exposed DAP,
using a four layer PCB for heat sinking. The thermal vias connect the copper area directly under the exposed
DAP to the first internal copper plane only. See JEDEC standards EIA/JESD51-5 and EIA/JESD51-7 for more
information.
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LP38511-ADJ
Submit Documentation Feedback
11