LM3S2D93 Datasheet, PDF (11/1201 Pages) Texas Instruments – Stellaris® LM3S2D93 Microcontroller

Stellaris^® LM3S2D93 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S2D93 Microcontroller High-Level Block Diagram ............................... 39
Figure 2-1. CPU Block Diagram ............................................................................................. 62
Figure 2-2. TPIU Block Diagram ............................................................................................ 63
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 65
Figure 2-4. Bit-Band Mapping ................................................................................................ 86
Figure 2-5. Data Storage ....................................................................................................... 87
Figure 2-6. Vector Table ........................................................................................................ 93
Figure 2-7. Exception Stack Frame ........................................................................................ 95
Figure 3-1. SRD Use Example ............................................................................................. 109
Figure 4-1. JTAG Module Block Diagram .............................................................................. 170
Figure 4-2. Test Access Port State Machine ......................................................................... 173
Figure 4-3. IDCODE Register Format ................................................................................... 179
Figure 4-4. BYPASS Register Format ................................................................................... 179
Figure 4-5. Boundary Scan Register Format ......................................................................... 180
Figure 5-1. Basic RST Configuration .................................................................................... 184
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 184
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 185
Figure 5-4. Power Architecture ............................................................................................ 188
Figure 5-5. Main Clock Tree ................................................................................................ 191
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 288
Figure 6-2. Using a Crystal as the Hibernation Clock Source ................................................. 291
Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 291
Figure 7-1. Internal Memory Block Diagram .......................................................................... 314
Figure 8-1. μDMA Block Diagram ......................................................................................... 361
Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 367
Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 369
Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 370
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 372
Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 373
Figure 9-1. Digital I/O Pads ................................................................................................. 425
Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 426
Figure 9-3. GPIODATA Write Example ................................................................................. 427
Figure 9-4. GPIODATA Read Example ................................................................................. 427
Figure 10-1. EPI Block Diagram ............................................................................................. 478
Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 486
Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 486
Figure 10-4. SDRAM Write Cycle ........................................................................................... 487
Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 493
Figure 10-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 495
Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 496
Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 496
Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual
CSn .................................................................................................................. 497
Figure 10-10. Continuous Read Mode Accesses ...................................................................... 497
January 23, 2012
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Texas Instruments-Production Data