DRV8823-Q1 Datasheet, PDF (11/18 Pages) Texas Instruments – 4-BRIDGE SERIAL INTERFACE MOTOR DRIVER

DRV8823-Q1
www.ti.com
SLVSBH2A – JUNE 2012 – REVISED JULY 2012
Protection Circuits
The DRV8823-Q1 device is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
All of the drivers in the DRV8823-Q1 device are protected with an overcurrent protection (OCP) circuit.
The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive form each output
FET if the current through it exceeds a preset level. This circuit limits the current to a level that is safe to prevent
damage to the FET.
A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer than
a preset period, all drivers in the device are disabled.
The device is re-enabled upon the removal and re-application of power at the VM pins.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all drivers in the device are shut down.
The device remains disabled until the die temperature falls to a safe level. After the temperature falls, the device
may be re-enabled upon the removal and re-application of power at the VM pin.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device is disabled. Operation resumes when VM rises above the UVLO threshold. The indexer logic is reset to its
initial condition in the event of an undervoltage lockout.
Shoot-Through Current Prevention
The gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot-through current)
during transitions.
Serial Data Transmission
Data transfers consist of 16 bits of serial data, shifted into the SDATA pin LSB first.
On serial writes to the DRV8823-Q1 device, additional clock edges following the final data bit continues to shift
data bits into the data register; therefore, the last 16 bits presented are latched and used.
One of two registers is selected by setting bits in an address field in the four upper bits in the serial data
transferred (ADDR in the tables below). One 16-bit register is used to control motor number 1 (bridges A and B),
and a second 16-bit register is used to control motor 2 (bridges C and D).
Data can only be transferred into the serial interface if the SCS input pin is active high.
Data is initially clocked in to a temporary holding register. This data is latched into the motor driver on the rising
edge of the SSTB pin. If the SSTB pin is tied high at all times, the data will be latched in after all 16 bits have
been transferred.
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DRV8823-Q1
Submit Documentation Feedback
11