ADS774H Datasheet, PDF(11/23 Page) Texas Instruments – Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER

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ADS774H

www.ti.com ................................................................................................................................................................................................ SBAS443 â AUGUST 2009

THEORY OF OPERATION

OVERVIEW

CONVERSION

In the ADS774H, the advantages of advanced CMOS

technology (such as high logic density, stable

capacitors, and precision analog switches) produce a

fast, low-power ADC with internal sample/hold.

The charge-redistribution successive-approximation

circuitry converts analog input voltages into digital

words.

A simple example of a charge-redistribution ADC with

only three bits is shown in Figure 11.

SAMPLING

While sampling, the capacitor array switch for the

MSB capacitor (S1) is in position S, so that the

charge on the MSB capacitor is proportional to the

voltage level of the analog input signal. The

remaining array switches (S2 and S3) are set to

position G. Switch SC is closed, setting the

comparator input offset to zero.

When a conversion command is received, switch S1

opens to capture a charge on the MSB capacitor

proportional to the analog input level at the time of

the sampling command, and switch SC opens to float

the comparator input. The charge held in the

capacitor array can now be moved between the three

capacitors in the array by connecting switches S1, S2,

and S3 to either the R position (to connect to the

reference) or the G position (to connect to GND), thus

changing the voltage generated at the comparator

input.

During the first approximation, the MSB capacitor is

connected through switch S1 to the reference, while

switches S2 and S3 are connected to GND.

Depending on whether the comparator output is high

or low, the logic then latches S1 in position R or G.

Similarly, the second approximation is made by

connecting S2 to the reference and S3 to GND, and

latching S2 according to the output of the comparator.

After three successive approximation steps have

been made, the voltage level at the comparator is

within 1/2LSB of GND, and a digital word that

represents the analog input can be determined from

the positions of S1, S2 and S3.

Analog

Input

Comparator

Signal

Out

RG RG RG

Reference

Input

Figure 11. 3-Bit Charge Redistribution ADC

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