ADS6445_14 Datasheet, PDF (11/82 Pages) Texas Instruments – QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

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ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B – MAY 2007 – REVISED DECEMBER 2009
TIMING SPECIFICATIONS ⁽¹⁾ (continued)
Typical values are at 25°C, min and max values are across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP clock amplitude, C_L = 5 pF ⁽²⁾, I_O = 3.5 mA,
R_L = 100 Ω ⁽³⁾, no internal termination, unless otherwise noted.
PARAMETER
TEST
CONDITIONS
ADS6445
F_s = 125 MSPS
MIN TYP MAX
ADS6444
F_s = 105 MSPS
MIN TYP MAX
ADS6443
F_s = 80 MSPS
MIN TYP MAX
ADS6442
F_s = 65 MSPS
MIN TYP MAX
UNIT
Time for a
ADC Latency
(7)
sample to
propagate to
12
12
ADC outputs,
see Figure 1
12
12
Clock
cycles
Time to valid
data after
coming out of
100
100
100
global power
down
100 μs
Time to valid
Wake up time
data after input
clock is
100
100
100
re-started
100 μs
Time to valid
data after
coming out of
200
200
200
channel
standby
200
Clock
cycles
t_RISE Data rise
time
From –100 mV
to +100 mV
50 100 200
50 100
50 100 200
50 100 200 ps
t_FALL Data fall time From +100 mV
to –100 mV
50 100 200
50 100
50 100 200
50 100 200 ps
t_RISE
Bit clock and
frame clock
rise time
From –100mV
to +100mV
50 100 200 50 100
50 100 200
50 100 200 ps
t_FALL
Bit clock and
frame clock
fall time
From +100mV
to –100mV
50 100 200 50 100
50 100 200
50 100 200 ps
LVDS Bit
clock duty
cycle
45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55%
LVDS Frame
clock duty
cycle
47% 50% 53% 47% 50% 53% 47% 50% 53% 47% 50% 53%
(7) Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
shown in Table 27.
Copyright © 2007–2009, Texas Instruments Incorporated
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