ADS6445_14 Datasheet, PDF (1/82 Pages) Texas Instruments – QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

ADS6445, ADS6444
ADS6443, ADS6442
www.ti.com
SLAS531B – MAY 2007 – REVISED DECEMBER 2009
QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
Check for Samples: ADS6445, ADS6444, ADS6443, ADS6442
FEATURES
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• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5dB Coarse Gain and up to 6dB
Programmable Fine Gain for SFDR/SNR
Trade-Off
• Serialized LVDS Outputs with Programmable
Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude down to 400 mV_PP
• Internal Reference with External Reference
Support
• No External Decoupling Required for
References
• 3.3-V Analog and Digital Supply
• 64 QFN Package (9 mm × 9 mm)
• Pin Compatible 12-Bit Family (ADS642X -
SLAS532A)
• Feature Compatible Dual Channel Family
(ADS624X - SLAS542A, ADS644X - SLAS543A)
APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment
Table 1. ADS64XX Quad Channel Family
ADS644X
14 Bit
ADS642X
12 Bit
125 MSPS
ADS6445
ADS6425
105 MSPS 80 MSPS 65 MSPS
ADS6444 ADS6443 ADS6442
ADS6424 ADS6423 ADS6422
Table 2. Performance Summary
SFDR, dBc
Fin = 10MHz (0 dB gain)
Fin = 170MHz (3.5 dB gain)
Fin = 10MHz (0 dB gain)
SINAD, dBFS
Fin = 170MHz (3.5 dB gain)
Power, per channel, mW
ADS6445
87
79
73.4
68.3
420
ADS6444
91
83
73.4
69.3
340
ADS6443
92
84
74.2
69.4
300
ADS6442
93
84
74.3
70
265
DESCRIPTION
The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65
MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in
a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device
includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR.
In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing
receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and
bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and
internal termination options. These can be used to widen eye-openings and improve signal integrity, easing
capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated